From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58989) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ull4J-0000QR-B1 for qemu-devel@nongnu.org; Sun, 09 Jun 2013 15:14:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ull4H-0000hy-JQ for qemu-devel@nongnu.org; Sun, 09 Jun 2013 15:14:23 -0400 Received: from cantor2.suse.de ([195.135.220.15]:44424 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ull4H-0000hm-Bw for qemu-devel@nongnu.org; Sun, 09 Jun 2013 15:14:21 -0400 Received: from relay1.suse.de (unknown [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id EFC32A5230 for ; Sun, 9 Jun 2013 21:14:20 +0200 (CEST) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 9 Jun 2013 21:12:56 +0200 Message-Id: <1370805206-26574-30-git-send-email-afaerber@suse.de> In-Reply-To: <1370805206-26574-1-git-send-email-afaerber@suse.de> References: <1370805206-26574-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH qom-cpu 29/59] cputlb: Simplify cpu_tlb_reset_dirty_all() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= Use new qemu_for_each_cpu(). Signed-off-by: Andreas F=C3=A4rber --- cputlb.c | 35 ++++++++++++++++++++++++----------- 1 file changed, 24 insertions(+), 11 deletions(-) diff --git a/cputlb.c b/cputlb.c index f7cc4b4..748d0f6 100644 --- a/cputlb.c +++ b/cputlb.c @@ -173,24 +173,37 @@ static inline void tlb_update_dirty(CPUTLBEntry *tl= b_entry) } } =20 -void cpu_tlb_reset_dirty_all(ram_addr_t start1, ram_addr_t length) -{ - CPUArchState *env; +typedef struct CPUTLBResetDirtyData { + ram_addr_t start1; + ram_addr_t length; +} CPUTLBResetDirtyData; =20 - for (env =3D first_cpu; env !=3D NULL; env =3D env->next_cpu) { - int mmu_idx; +static void cpu_tlb_reset_dirty_one(CPUState *cpu, void *data) +{ + CPUTLBResetDirtyData *s =3D data; + CPUArchState *env =3D cpu->env_ptr; + int mmu_idx; =20 - for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { - unsigned int i; + for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { + unsigned int i; =20 - for (i =3D 0; i < CPU_TLB_SIZE; i++) { - tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i], - start1, length); - } + for (i =3D 0; i < CPU_TLB_SIZE; i++) { + tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i], + s->start1, s->length); } } } =20 +void cpu_tlb_reset_dirty_all(ram_addr_t start1, ram_addr_t length) +{ + CPUTLBResetDirtyData s =3D { + .start1 =3D start1, + .length =3D length, + }; + + qemu_for_each_cpu(cpu_tlb_reset_dirty_one, &s); +} + static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong v= addr) { if (tlb_entry->addr_write =3D=3D (vaddr | TLB_NOTDIRTY)) { --=20 1.8.1.4