From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59565) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ull4t-0001WF-1J for qemu-devel@nongnu.org; Sun, 09 Jun 2013 15:15:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ull4q-0000uw-6k for qemu-devel@nongnu.org; Sun, 09 Jun 2013 15:14:58 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 9 Jun 2013 21:13:24 +0200 Message-Id: <1370805206-26574-58-git-send-email-afaerber@suse.de> In-Reply-To: <1370805206-26574-1-git-send-email-afaerber@suse.de> References: <1370805206-26574-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH qom-cpu 57/59] cpu: Make first_cpu and next_cpu CPUState (WIP) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Anthony Liguori , Marcelo Tosatti , Igor Mitsyanko , Mark Langsdorf , Evgeny Voevodin , Riku Voipio , Alexander Graf , Gleb Natapov , Peter Crosthwaite , =?UTF-8?q?Andreas=20F=C3=A4rber?= , "open list:PReP" , Paul Brook , David Gibson , "open list:X86" , "Edgar E. Iglesias" , Maksim Kozlov , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno , Dmitry Solodkiy TODO: gdbstub TBD: linux-user thread_env Signed-off-by: Andreas F=C3=A4rber --- cpus.c | 15 +++++++++------ exec.c | 27 ++++++++++++++------------- gdbstub.c | 15 ++++++++------- hw/arm/boot.c | 10 +++++----- hw/arm/exynos4_boards.c | 4 ++-- hw/arm/highbank.c | 2 +- hw/arm/realview.c | 2 +- hw/arm/vexpress.c | 2 +- hw/arm/xilinx_zynq.c | 2 +- hw/i386/kvm/clock.c | 6 ++++-- hw/i386/kvmvapic.c | 5 +++-- hw/i386/pc.c | 11 ++++++----- hw/i386/pc_piix.c | 3 +-- hw/intc/sh_intc.c | 5 ++--- hw/isa/lpc_ich9.c | 2 +- hw/mips/mips_malta.c | 3 ++- hw/ppc/prep.c | 6 ++++-- hw/ppc/spapr.c | 12 ++++++------ include/exec/cpu-all.h | 2 +- include/exec/cpu-defs.h | 1 - include/qom/cpu.h | 2 ++ linux-user/main.c | 4 ++-- linux-user/syscall.c | 9 ++++++--- target-i386/arch_dump.c | 7 +++++-- target-i386/kvm.c | 8 +++++--- target-i386/misc_helper.c | 2 +- 26 files changed, 93 insertions(+), 74 deletions(-) diff --git a/cpus.c b/cpus.c index a0b8e6b..d16afba 100644 --- a/cpus.c +++ b/cpus.c @@ -60,7 +60,7 @@ =20 #endif /* CONFIG_LINUX */ =20 -static CPUArchState *next_cpu; +static CPUState *next_cpu; =20 static bool cpu_thread_is_idle(CPUState *cpu) { @@ -836,7 +836,7 @@ static void *qemu_tcg_cpu_thread_fn(void *arg) qemu_cond_signal(&qemu_cpu_cond); =20 /* wait for initial kick-off after machine start */ - while (ENV_GET_CPU(first_cpu)->stopped) { + while (first_cpu->stopped) { qemu_cond_wait(tcg_halt_cond, &qemu_global_mutex); =20 /* process any pending work */ @@ -933,7 +933,7 @@ void qemu_mutex_lock_iothread(void) } else { iothread_requesting_mutex =3D true; if (qemu_mutex_trylock(&qemu_global_mutex)) { - qemu_cpu_kick_thread(ENV_GET_CPU(first_cpu)); + qemu_cpu_kick_thread(first_cpu); qemu_mutex_lock(&qemu_global_mutex); } iothread_requesting_mutex =3D false; @@ -1162,8 +1162,8 @@ static void tcg_exec_all(void) next_cpu =3D first_cpu; } for (; next_cpu !=3D NULL && !exit_request; next_cpu =3D next_cpu->n= ext_cpu) { - CPUArchState *env =3D next_cpu; - CPUState *cpu =3D ENV_GET_CPU(env); + CPUState *cpu =3D next_cpu; + CPUArchState *env =3D cpu->env_ptr; =20 qemu_clock_enable(vm_clock, (env->singlestep_enabled & SSTEP_NOTIMER) =3D=3D= 0); @@ -1213,7 +1213,10 @@ typedef struct QMPQueryCPUs { static void qmp_query_one_cpu(CPUState *cpu, void *data) { QMPQueryCPUs *s =3D data; +#if defined(TARGET_I386) || defined(TARGET_PPC) || defined(TARGET_SPARC)= || \ + defined(TARGET_MIPS) CPUArchState *env =3D cpu->env_ptr; +#endif CpuInfoList *info; =20 cpu_synchronize_state(cpu); @@ -1221,7 +1224,7 @@ static void qmp_query_one_cpu(CPUState *cpu, void *= data) info =3D g_malloc0(sizeof(*info)); info->value =3D g_malloc0(sizeof(*info->value)); info->value->CPU =3D cpu->cpu_index; - info->value->current =3D (env =3D=3D first_cpu); + info->value->current =3D (cpu =3D=3D first_cpu); info->value->halted =3D cpu->halted; info->value->thread_id =3D cpu->thread_id; #if defined(TARGET_I386) diff --git a/exec.c b/exec.c index d2e790c..122a3c1 100644 --- a/exec.c +++ b/exec.c @@ -70,7 +70,7 @@ static MemoryRegion io_mem_unassigned, io_mem_subpage_r= am; =20 #endif =20 -CPUArchState *first_cpu; +CPUState *first_cpu; /* current CPU in the current thread. It is only valid inside cpu_exec() */ DEFINE_TLS(CPUState *,cpu_single_cpu); @@ -289,11 +289,12 @@ CPUState *qemu_get_cpu(int index) =20 void qemu_for_each_cpu(void (*func)(CPUState *cpu, void *data), void *da= ta) { - CPUArchState *env =3D first_cpu; + CPUState *cpu; =20 - while (env) { - func(ENV_GET_CPU(env), data); - env =3D env->next_cpu; + cpu =3D first_cpu; + while (cpu) { + func(cpu, data); + cpu =3D cpu->next_cpu; } } =20 @@ -301,17 +302,17 @@ void cpu_exec_init(CPUArchState *env) { CPUState *cpu =3D ENV_GET_CPU(env); CPUClass *cc =3D CPU_GET_CLASS(cpu); - CPUArchState **penv; + CPUState **pcpu; int cpu_index; =20 #if defined(CONFIG_USER_ONLY) cpu_list_lock(); #endif - env->next_cpu =3D NULL; - penv =3D &first_cpu; + cpu->next_cpu =3D NULL; + pcpu =3D &first_cpu; cpu_index =3D 0; - while (*penv !=3D NULL) { - penv =3D &(*penv)->next_cpu; + while (*pcpu !=3D NULL) { + pcpu =3D &(*pcpu)->next_cpu; cpu_index++; } cpu->cpu_index =3D cpu_index; @@ -321,7 +322,7 @@ void cpu_exec_init(CPUArchState *env) #ifndef CONFIG_USER_ONLY cpu->thread_id =3D qemu_get_thread_id(); #endif - *penv =3D env; + *pcpu =3D cpu; #if defined(CONFIG_USER_ONLY) cpu_list_unlock(); #endif @@ -560,7 +561,7 @@ void cpu_abort(CPUArchState *env, const char *fmt, ..= .) CPUArchState *cpu_copy(CPUArchState *env) { CPUArchState *new_env =3D cpu_init(env->cpu_model_str); - CPUArchState *next_cpu =3D new_env->next_cpu; + CPUState *next_cpu =3D ENV_GET_CPU(new_env)->next_cpu; #if defined(TARGET_HAS_ICE) CPUBreakpoint *bp; CPUWatchpoint *wp; @@ -569,7 +570,7 @@ CPUArchState *cpu_copy(CPUArchState *env) memcpy(new_env, env, sizeof(CPUArchState)); =20 /* Preserve chaining. */ - new_env->next_cpu =3D next_cpu; + ENV_GET_CPU(new_env)->next_cpu =3D next_cpu; =20 /* Clone all break/watchpoints. Note: Once we support ptrace with hw-debug register access, make = sure diff --git a/gdbstub.c b/gdbstub.c index 9400abd..e0cd25b 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -1836,6 +1836,7 @@ static const char *get_feature_xml(const char *p, c= onst char **newp) /* Generate the XML description for this CPU. */ if (!target_xml[0]) { GDBRegisterState *r; + CPUArchState *env =3D first_cpu->env_ptr; =20 snprintf(target_xml, sizeof(target_xml), "" @@ -1844,7 +1845,7 @@ static const char *get_feature_xml(const char *p, c= onst char **newp) "", GDB_CORE_XML); =20 - for (r =3D first_cpu->gdb_regs; r; r =3D r->next) { + for (r =3D env->gdb_regs; r; r =3D r->next) { pstrcat(target_xml, sizeof(target_xml), "xml); pstrcat(target_xml, sizeof(target_xml), "\"/>"); @@ -2438,7 +2439,7 @@ static int gdb_handle_packet(GDBState *s, const cha= r *line_buf) put_packet(s, "QC1"); break; } else if (strcmp(p,"fThreadInfo") =3D=3D 0) { - s->query_cpu =3D first_cpu; + s->query_cpu =3D first_cpu->env_ptr; goto report_cpuinfo; } else if (strcmp(p,"sThreadInfo") =3D=3D 0) { report_cpuinfo: @@ -2446,7 +2447,7 @@ static int gdb_handle_packet(GDBState *s, const cha= r *line_buf) snprintf(buf, sizeof(buf), "m%x", cpu_index(ENV_GET_CPU(s->query_cpu))); put_packet(s, buf); - s->query_cpu =3D s->query_cpu->next_cpu; + s->query_cpu =3D ENV_GET_CPU(s->query_cpu)->next_cpu->en= v_ptr; } else put_packet(s, "l"); break; @@ -2913,8 +2914,8 @@ static void gdb_accept(void) socket_set_nodelay(fd); =20 s =3D g_malloc0(sizeof(GDBState)); - s->c_cpu =3D first_cpu; - s->g_cpu =3D first_cpu; + s->c_cpu =3D first_cpu->env_ptr; + s->g_cpu =3D first_cpu->env_ptr; s->fd =3D fd; gdb_has_xml =3D 0; =20 @@ -3098,8 +3099,8 @@ int gdbserver_start(const char *device) mon_chr =3D s->mon_chr; memset(s, 0, sizeof(GDBState)); } - s->c_cpu =3D first_cpu; - s->g_cpu =3D first_cpu; + s->c_cpu =3D first_cpu->env_ptr; + s->g_cpu =3D first_cpu->env_ptr; s->chr =3D chr; s->state =3D chr ? RS_IDLE : RS_INACTIVE; s->mon_chr =3D mon_chr; diff --git a/hw/arm/boot.c b/hw/arm/boot.c index f451529..ad13d3f 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -329,7 +329,7 @@ static void do_cpu_reset(void *opaque) env->regs[15] =3D info->entry & 0xfffffffe; env->thumb =3D info->entry & 1; } else { - if (env =3D=3D first_cpu) { + if (CPU(cpu) =3D=3D first_cpu) { env->regs[15] =3D info->loader_start; if (!info->dtb_filename) { if (old_param) { @@ -347,7 +347,7 @@ static void do_cpu_reset(void *opaque) =20 void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) { - CPUARMState *env =3D &cpu->env; + CPUState *cs =3D CPU(cpu); int kernel_size; int initrd_size; int n; @@ -472,9 +472,9 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_inf= o *info) } info->is_linux =3D is_linux; =20 - for (; env; env =3D env->next_cpu) { - cpu =3D arm_env_get_cpu(env); - env->boot_info =3D info; + for (; cs; cs =3D cs->next_cpu) { + cpu =3D ARM_CPU(cs); + cpu->env.boot_info =3D info; qemu_register_reset(do_cpu_reset, cpu); } } diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c index 74f110b..7c90b2d 100644 --- a/hw/arm/exynos4_boards.c +++ b/hw/arm/exynos4_boards.c @@ -131,7 +131,7 @@ static void nuri_init(QEMUMachineInitArgs *args) { exynos4_boards_init_common(args, EXYNOS4_BOARD_NURI); =20 - arm_load_kernel(arm_env_get_cpu(first_cpu), &exynos4_board_binfo); + arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo); } =20 static void smdkc210_init(QEMUMachineInitArgs *args) @@ -141,7 +141,7 @@ static void smdkc210_init(QEMUMachineInitArgs *args) =20 lan9215_init(SMDK_LAN9118_BASE_ADDR, qemu_irq_invert(s->irq_table[exynos4210_get_irq(37, 1)])); - arm_load_kernel(arm_env_get_cpu(first_cpu), &exynos4_board_binfo); + arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo); } =20 static QEMUMachine exynos4_machines[EXYNOS4_NUM_OF_BOARDS] =3D { diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index 4405dbd..1d28842 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -321,7 +321,7 @@ static void highbank_init(QEMUMachineInitArgs *args) highbank_binfo.loader_start =3D 0; highbank_binfo.write_secondary_boot =3D hb_write_secondary; highbank_binfo.secondary_cpu_reset_hook =3D hb_reset_secondary; - arm_load_kernel(arm_env_get_cpu(first_cpu), &highbank_binfo); + arm_load_kernel(ARM_CPU(first_cpu), &highbank_binfo); } =20 static QEMUMachine highbank_machine =3D { diff --git a/hw/arm/realview.c b/hw/arm/realview.c index d6f47bf..05dc3f3 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -329,7 +329,7 @@ static void realview_init(QEMUMachineInitArgs *args, realview_binfo.nb_cpus =3D smp_cpus; realview_binfo.board_id =3D realview_board_id[board_type]; realview_binfo.loader_start =3D (board_type =3D=3D BOARD_PB_A8 ? 0x7= 0000000 : 0); - arm_load_kernel(arm_env_get_cpu(first_cpu), &realview_binfo); + arm_load_kernel(ARM_CPU(first_cpu), &realview_binfo); } =20 static void realview_eb_init(QEMUMachineInitArgs *args) diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index a077c62..c8f2890 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -519,7 +519,7 @@ static void vexpress_common_init(const VEDBoardInfo *= daughterboard, vexpress_binfo.smp_loader_start =3D map[VE_SRAM]; vexpress_binfo.smp_bootreg_addr =3D map[VE_SYSREGS] + 0x30; vexpress_binfo.gic_cpu_if_addr =3D daughterboard->gic_cpu_if_addr; - arm_load_kernel(arm_env_get_cpu(first_cpu), &vexpress_binfo); + arm_load_kernel(ARM_CPU(first_cpu), &vexpress_binfo); } =20 static void vexpress_a9_init(QEMUMachineInitArgs *args) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 4602a6f..f73eeed 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -226,7 +226,7 @@ static void zynq_init(QEMUMachineInitArgs *args) zynq_binfo.nb_cpus =3D 1; zynq_binfo.board_id =3D 0xd32; zynq_binfo.loader_start =3D 0; - arm_load_kernel(arm_env_get_cpu(first_cpu), &zynq_binfo); + arm_load_kernel(ARM_CPU(first_cpu), &zynq_binfo); } =20 static QEMUMachine zynq_machine =3D { diff --git a/hw/i386/kvm/clock.c b/hw/i386/kvm/clock.c index eaeb0ff..cece046 100644 --- a/hw/i386/kvm/clock.c +++ b/hw/i386/kvm/clock.c @@ -132,9 +132,11 @@ static const TypeInfo kvmclock_info =3D { /* Note: Must be called after VCPU initialization. */ void kvmclock_create(void) { + X86CPU *cpu =3D X86_CPU(first_cpu); + if (kvm_enabled() && - first_cpu->features[FEAT_KVM] & ((1ULL << KVM_FEATURE_CLOCKSOURC= E) | - (1ULL << KVM_FEATURE_CLOCKSOURC= E2))) { + cpu->env.features[FEAT_KVM] & ((1ULL << KVM_FEATURE_CLOCKSOURCE)= | + (1ULL << KVM_FEATURE_CLOCKSOURCE2= ))) { sysbus_create_simple("kvmclock", -1, NULL); } } diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c index dfb1085..0dd677a 100644 --- a/hw/i386/kvmvapic.c +++ b/hw/i386/kvmvapic.c @@ -720,8 +720,9 @@ static int vapic_init(SysBusDevice *dev) static void do_vapic_enable(void *data) { VAPICROMState *s =3D data; + X86CPU *cpu =3D X86_CPU(first_cpu); =20 - vapic_enable(s, first_cpu); + vapic_enable(s, &cpu->env); } =20 static int vapic_post_load(void *opaque, int version_id) @@ -744,7 +745,7 @@ static int vapic_post_load(void *opaque, int version_= id) } if (s->state =3D=3D VAPIC_ACTIVE) { if (smp_cpus =3D=3D 1) { - run_on_cpu(ENV_GET_CPU(first_cpu), do_vapic_enable, s); + run_on_cpu(first_cpu, do_vapic_enable, s); } else { zero =3D g_malloc0(s->rom_state.vapic_size); cpu_physical_memory_rw(s->vapic_paddr, zero, diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 28c9c6e..e4e0ea1 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -160,8 +160,9 @@ void cpu_smm_register(cpu_set_smm_t callback, void *a= rg) =20 void cpu_smm_update(CPUX86State *env) { - if (smm_set && smm_arg && env =3D=3D first_cpu) + if (smm_set && smm_arg && CPU(x86_env_get_cpu(env)) =3D=3D first_cpu= ) { smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg); + } } =20 =20 @@ -195,13 +196,14 @@ static void pic_irq_request_apic_one(CPUState *cs, = void *data) =20 static void pic_irq_request(void *opaque, int irq, int level) { - CPUX86State *env =3D first_cpu; + CPUState *cs =3D first_cpu; + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; =20 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); if (env->apic_state) { qemu_for_each_cpu(pic_irq_request_apic_one, &level); } else { - CPUState *cs =3D CPU(x86_env_get_cpu(env)); if (level) { cpu_interrupt(cs, CPU_INTERRUPT_HARD); } else { @@ -1203,8 +1205,7 @@ void pc_basic_device_init(ISABus *isa_bus, qemu_irq= *gsi, } } =20 - a20_line =3D qemu_allocate_irqs(handle_a20_line_change, - x86_env_get_cpu(first_cpu), 2); + a20_line =3D qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2= ); i8042 =3D isa_create_simple(isa_bus, "i8042"); i8042_setup_a20_line(i8042, &a20_line[0]); if (!no_vmport) { diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 69eb2a1..c454495 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -213,8 +213,7 @@ static void pc_init1(MemoryRegion *system_memory, if (pci_enabled && acpi_enabled) { i2c_bus *smbus; =20 - smi_irq =3D qemu_allocate_irqs(pc_acpi_smi_interrupt, - x86_env_get_cpu(first_cpu), 1); + smi_irq =3D qemu_allocate_irqs(pc_acpi_smi_interrupt, first_cpu,= 1); /* TODO: Populate SPD eeprom data. */ smbus =3D piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, gsi[9], *smi_irq, diff --git a/hw/intc/sh_intc.c b/hw/intc/sh_intc.c index 050bfb6..f1138e3 100644 --- a/hw/intc/sh_intc.c +++ b/hw/intc/sh_intc.c @@ -42,16 +42,15 @@ void sh_intc_toggle_source(struct intc_source *source= , pending_changed =3D 1; =20 if (pending_changed) { - CPUState *cpu =3D CPU(sh_env_get_cpu(first_cpu)); if (source->pending) { source->parent->pending++; if (source->parent->pending =3D=3D 1) { - cpu_interrupt(cpu, CPU_INTERRUPT_HARD); + cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD); } } else { source->parent->pending--; if (source->parent->pending =3D=3D 0) { - cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD); + cpu_reset_interrupt(first_cpu, CPU_INTERRUPT_HARD); } } } diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 667e882..69e1f50 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -380,7 +380,7 @@ static void ich9_apm_ctrl_changed(uint32_t val, void = *arg) =20 /* SMI_EN =3D PMBASE + 30. SMI control and enable register */ if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) { - cpu_interrupt(CPU(x86_env_get_cpu(first_cpu)), CPU_INTERRUPT_SMI= ); + cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI); } } =20 diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 4fc611c..adea146 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -844,7 +844,8 @@ void mips_malta_init(QEMUMachineInitArgs *args) cpu_mips_clock_init(env); qemu_register_reset(main_cpu_reset, cpu); } - env =3D first_cpu; + cpu =3D MIPS_CPU(first_cpu); + env =3D &cpu->env; =20 /* allocate RAM */ if (ram_size > (256 << 20)) { diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c index 83ceb7b..245ce7d 100644 --- a/hw/ppc/prep.c +++ b/hw/ppc/prep.c @@ -594,8 +594,9 @@ static void ppc_prep_init(QEMUMachineInitArgs *args) /* PCI -> ISA bridge */ pci =3D pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378"); cpu_exit_irq =3D qemu_allocate_irqs(cpu_request_exit, NULL, 1); + cpu =3D POWERPC_CPU(first_cpu); qdev_connect_gpio_out(&pci->qdev, 0, - first_cpu->irq_inputs[PPC6xx_INPUT_INT]); + cpu->env.irq_inputs[PPC6xx_INPUT_INT]); qdev_connect_gpio_out(&pci->qdev, 1, *cpu_exit_irq); sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev,= 9)); sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev,= 11)); @@ -639,7 +640,8 @@ static void ppc_prep_init(QEMUMachineInitArgs *args) } isa_create_simple(isa_bus, "i8042"); =20 - sysctrl->reset_irq =3D first_cpu->irq_inputs[PPC6xx_INPUT_HRESET]; + cpu =3D POWERPC_CPU(first_cpu); + sysctrl->reset_irq =3D cpu->env.irq_inputs[PPC6xx_INPUT_HRESET]; /* System control ports */ register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl); register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl)= ; diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index c8461da..e7afaea 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -661,7 +661,7 @@ static void spapr_reset_htab(sPAPREnvironment *spapr) =20 static void ppc_spapr_reset(void) { - CPUState *first_cpu_cpu; + PowerPCCPU *first_ppc_cpu; =20 /* Reset the hash table & recalc the RMA */ spapr_reset_htab(spapr); @@ -673,11 +673,11 @@ static void ppc_spapr_reset(void) spapr->rtas_size); =20 /* Set up the entry state */ - first_cpu_cpu =3D ENV_GET_CPU(first_cpu); - first_cpu->gpr[3] =3D spapr->fdt_addr; - first_cpu->gpr[5] =3D 0; - first_cpu_cpu->halted =3D 0; - first_cpu->nip =3D spapr->entry_point; + first_ppc_cpu =3D POWERPC_CPU(first_cpu); + first_ppc_cpu->env.gpr[3] =3D spapr->fdt_addr; + first_ppc_cpu->env.gpr[5] =3D 0; + first_cpu->halted =3D 0; + first_ppc_cpu->env.nip =3D spapr->entry_point; =20 } =20 diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index a0ca585..b8a9d3a 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -356,7 +356,7 @@ CPUArchState *cpu_copy(CPUArchState *env); =20 void QEMU_NORETURN cpu_abort(CPUArchState *env, const char *fmt, ...) GCC_FMT_ATTR(2, 3); -extern CPUArchState *first_cpu; +extern CPUState *first_cpu; DECLARE_TLS(CPUState *,cpu_single_cpu); #define cpu_single_cpu tls_var(cpu_single_cpu) =20 diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 031a26c..d8f116c 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -181,7 +181,6 @@ typedef struct CPUWatchpoint { sigjmp_buf jmp_env; = \ int exception_index; = \ = \ - CPUArchState *next_cpu; /* next CPU sharing TB cache */ = \ /* user data */ = \ void *opaque; = \ = \ diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 814d067..d77b903 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -113,6 +113,7 @@ struct kvm_run; * CPU and return to its top level loop. * @env_ptr: Pointer to subclass-specific CPUArchState field. * @current_tb: Currently executing TB. + * @next_cpu: Next CPU sharing TB cache. * @kvm_fd: vCPU file descriptor for KVM. * * State of one CPU core or thread. @@ -145,6 +146,7 @@ struct CPUState { =20 void *env_ptr; /* CPUArchState */ struct TranslationBlock *current_tb; + CPUState *next_cpu; =20 int kvm_fd; bool kvm_vcpu_dirty; diff --git a/linux-user/main.c b/linux-user/main.c index 5ced658..647c764 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -120,8 +120,8 @@ void fork_end(int child) if (child) { /* Child processes created by fork() only have a single thread. Discard information about the parent threads. */ - first_cpu =3D thread_env; - thread_env->next_cpu =3D NULL; + first_cpu =3D ENV_GET_CPU(thread_env); + first_cpu->next_cpu =3D NULL; pending_cpus =3D 0; pthread_mutex_init(&exclusive_lock, NULL); pthread_mutex_init(&cpu_list_mutex, NULL); diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 0099d64..38c1f5a 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -5193,6 +5193,9 @@ abi_long do_syscall(void *cpu_env, int num, abi_lon= g arg1, abi_long arg5, abi_long arg6, abi_long arg7, abi_long arg8) { +#ifdef CONFIG_USE_NPTL + CPUState *cpu =3D ENV_GET_CPU(cpu_env); +#endif abi_long ret; struct stat st; struct statfs stfs; @@ -5215,13 +5218,13 @@ abi_long do_syscall(void *cpu_env, int num, abi_l= ong arg1, be disabling signals. */ if (first_cpu->next_cpu) { TaskState *ts; - CPUArchState **lastp; - CPUArchState *p; + CPUState **lastp; + CPUState *p; =20 cpu_list_lock(); lastp =3D &first_cpu; p =3D first_cpu; - while (p && p !=3D (CPUArchState *)cpu_env) { + while (p && p !=3D cpu) { lastp =3D &p->next_cpu; p =3D p->next_cpu; } diff --git a/target-i386/arch_dump.c b/target-i386/arch_dump.c index 83898cd..d133228 100644 --- a/target-i386/arch_dump.c +++ b/target-i386/arch_dump.c @@ -185,7 +185,8 @@ int x86_cpu_write_elf64_note(WriteCoreDumpFunction f,= CPUState *cs, X86CPU *cpu =3D X86_CPU(cs); int ret; #ifdef TARGET_X86_64 - bool lma =3D !!(first_cpu->hflags & HF_LMA_MASK); + X86CPU *first_x86_cpu =3D X86_CPU(first_cpu); + bool lma =3D !!(first_x86_cpu->env.hflags & HF_LMA_MASK); =20 if (lma) { ret =3D x86_64_write_elf64_note(f, &cpu->env, cpuid, opaque); @@ -394,7 +395,9 @@ int cpu_get_dump_info(ArchDumpInfo *info) RAMBlock *block; =20 #ifdef TARGET_X86_64 - lma =3D !!(first_cpu->hflags & HF_LMA_MASK); + X86CPU *first_x86_cpu =3D X86_CPU(first_cpu); + + lma =3D !!(first_x86_cpu->env.hflags & HF_LMA_MASK); #endif =20 if (lma) { diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 39f4fbb..cc3dcec 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -345,20 +345,22 @@ int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, = void *addr) =20 int kvm_arch_on_sigbus(int code, void *addr) { - if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code =3D=3D BUS_MCEE= RR_AO) { + X86CPU *cpu =3D X86_CPU(first_cpu); + + if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code =3D=3D BUS_MCEERR= _AO) { ram_addr_t ram_addr; hwaddr paddr; =20 /* Hope we are lucky for AO MCE */ if (qemu_ram_addr_from_host(addr, &ram_addr) || - !kvm_physical_memory_addr_from_host(CPU(first_cpu)->kvm_stat= e, + !kvm_physical_memory_addr_from_host(first_cpu->kvm_state, addr, &paddr)) { fprintf(stderr, "Hardware memory error for memory used by " "QEMU itself instead of guest system!: %p\n", addr); return 0; } kvm_hwpoison_page_add(ram_addr); - kvm_mce_inject(x86_env_get_cpu(first_cpu), paddr, code); + kvm_mce_inject(X86_CPU(first_cpu), paddr, code); } else { if (code =3D=3D BUS_MCEERR_AO) { return 0; diff --git a/target-i386/misc_helper.c b/target-i386/misc_helper.c index ec834fc..bac975b 100644 --- a/target-i386/misc_helper.c +++ b/target-i386/misc_helper.c @@ -597,7 +597,7 @@ void helper_mwait(CPUX86State *env, int next_eip_adde= nd) cpu =3D x86_env_get_cpu(env); cs =3D CPU(cpu); /* XXX: not complete but not completely erroneous */ - if (cs->cpu_index !=3D 0 || env->next_cpu !=3D NULL) { + if (cs->cpu_index !=3D 0 || cs->next_cpu !=3D NULL) { /* more than one CPU: do not sleep because another CPU may wake this one */ } else { --=20 1.8.1.4