From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46906) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UodVG-0006ii-AZ for qemu-devel@nongnu.org; Mon, 17 Jun 2013 13:46:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UodVC-0003tD-RZ for qemu-devel@nongnu.org; Mon, 17 Jun 2013 13:46:06 -0400 Sender: Richard Henderson From: Richard Henderson Date: Mon, 17 Jun 2013 10:45:26 -0700 Message-Id: <1371491129-30246-2-git-send-email-rth@twiddle.net> In-Reply-To: <1371491129-30246-1-git-send-email-rth@twiddle.net> References: <1371491129-30246-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PULL 1/4] tcg-ppc64: Fix RLDCL opcode List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aliguori@us.ibm.com, Anton Blanchard , qemu-stable@nongnu.org From: Anton Blanchard The rldcl instruction doesn't have an sh field, so the minor opcode is shifted 1 bit. We were using the XO30 macro which shifted the minor opcode 2 bits. Remove XO30 and add MD30 and MDS30 macros which match the Power ISA categories. Cc: qemu-stable@nongnu.org Signed-off-by: Anton Blanchard Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 0fcf2b5..c7c0b8f 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -308,7 +308,8 @@ static int tcg_target_const_match (tcg_target_long val, #define OPCD(opc) ((opc)<<26) #define XO19(opc) (OPCD(19)|((opc)<<1)) -#define XO30(opc) (OPCD(30)|((opc)<<2)) +#define MD30(opc) (OPCD(30)|((opc)<<2)) +#define MDS30(opc) (OPCD(30)|((opc)<<1)) #define XO31(opc) (OPCD(31)|((opc)<<1)) #define XO58(opc) (OPCD(58)|(opc)) #define XO62(opc) (OPCD(62)|(opc)) @@ -354,10 +355,10 @@ static int tcg_target_const_match (tcg_target_long val, #define RLWINM OPCD( 21) #define RLWNM OPCD( 23) -#define RLDICL XO30( 0) -#define RLDICR XO30( 1) -#define RLDIMI XO30( 3) -#define RLDCL XO30( 8) +#define RLDICL MD30( 0) +#define RLDICR MD30( 1) +#define RLDIMI MD30( 3) +#define RLDCL MDS30( 8) #define BCLR XO19( 16) #define BCCTR XO19(528) -- 1.8.1.4