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From: Torvald Riegel <triegel@redhat.com>
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Date: Wed, 19 Jun 2013 09:11:36 +0200
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Subject: Re: [Qemu-devel] Java volatile vs. C11 seq_cst (was Re: [PATCH v2
 1/2] add a header file for atomic operations)
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To: paulmck@linux.vnet.ibm.com
Cc: Susmit.Sarkar@cl.cam.ac.uk, Andrew Haley <aph@redhat.com>, qemu-devel@nongnu.org, Liu Ping Fan <qemulist@gmail.com>, Anthony Liguori <anthony@codemonkey.ws>, luc.maranget@inria.fr, Paolo Bonzini <pbonzini@redhat.com>, Peter.Sewell@cl.cam.ac.uk, Richard Henderson <rth@twiddle.net>

On Tue, 2013-06-18 at 18:53 -0700, Paul E. McKenney wrote:
> On Tue, Jun 18, 2013 at 05:37:42PM +0200, Torvald Riegel wrote:
> > On Tue, 2013-06-18 at 07:50 -0700, Paul E. McKenney wrote:
> > > First, I am not a fan of SC, mostly because there don't seem to be many
> > > (any?) production-quality algorithms that need SC.  But if you really
> > > want to take a parallel-programming trip back to the 1980s, let's go!  ;-)
> > 
> > Dekker-style mutual exclusion is useful for things like read-mostly
> > multiple-reader single-writer locks, or similar "asymmetric" cases of
> > synchronization.  SC fences are needed for this.
> 
> They definitely need Power hwsync rather than lwsync, but they need
> fewer fences than would be emitted by slavishly following either of the
> SC recipes for Power.  (Another example needing store-to-load ordering
> is hazard pointers.)

The C++11 seq-cst fence expands to hwsync; combined with a relaxed
store / load, that should be minimal.  Or are you saying that on Power,
there is a weaker HW barrier available that still constrains store-load
reordering sufficiently?


Torvald