Re: [Qemu-devel] [PATCH 1/3] spapr pci msi: rework

[Benjamin Herrenschmidt <benh@kernel.crashing.org>]

On Fri, 2013-06-21 at 06:58 -0500, Anthony Liguori wrote:
> > I do not understand the question, really. Here we are emulating pHyp which
> > is not real hardware and never pretended to be. Our guests do not touch MSI
> > records in the config space and use RTAS MSI calls instead.
> 
> But RTAS is implemented as guest code.  I suspect it's doing region
> access to generate the actual MSI events.

No, not really.

On pHyp, RTAS just gets the list of MSIs for the slot from pHyp using private
hypercalls, including the MSI address.

Note that in HW the MSI address is specific to a PCI host bridge, ie, you have 6
bridges, they may all 6 provide the same addresses to the device though they decode
them to different PE's (protection domains).

But it doesn't matter. From a PAPR guest perspective, indeed, we don't care,
*except* for a hack that went upstream in 3.10 that tries to enforce 32-bit
MSIs on broken AMD video cards and makes assumptions based on the PCIe bus speed
in the device-tree :-) However we shouldn't hit that.

In any case, if Alexey was to actually emulate our real HW, just having the address
+ data is not enough to identify a specific interrupt since each PHB will have
it's own domain there.

Thus the host bridge must be passed down the call at the very least.

>From there, the way we internally generate and decode those address/data in qemu
is of no relevance since PAPR being paravirtualized, the guest doesn't care.

Ben.