From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35348) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Urwhh-0007LJ-Ey for qemu-devel@nongnu.org; Wed, 26 Jun 2013 16:52:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Urwhe-0000on-OJ for qemu-devel@nongnu.org; Wed, 26 Jun 2013 16:52:37 -0400 Received: from mail-pa0-x235.google.com ([2607:f8b0:400e:c03::235]:39420) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Urwhe-0000og-Hp for qemu-devel@nongnu.org; Wed, 26 Jun 2013 16:52:34 -0400 Received: by mail-pa0-f53.google.com with SMTP id tj12so74334pac.12 for ; Wed, 26 Jun 2013 13:52:33 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Wed, 26 Jun 2013 13:52:09 -0700 Message-Id: <1372279929-28836-10-git-send-email-rth@twiddle.net> In-Reply-To: <1372279929-28836-1-git-send-email-rth@twiddle.net> References: <1372279929-28836-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v2 9/9] tcg-arm: Use AT_PLATFORM to detect the host ISA List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: blauwirbel@gmail.com, claudio.fontana@huawei.com, aurelien@aurel32.net With this we can generate armv7 insns even when the OS compiles for a lower common denominator. The macros are arranged so that when we do compile for a given ISA, all of the runtime checks for that ISA are optimized away. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index 763b173..a46d2e0 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -41,9 +41,11 @@ # endif #endif -#define use_armv5_instructions (__ARM_ARCH >= 5) -#define use_armv6_instructions (__ARM_ARCH >= 6) -#define use_armv7_instructions (__ARM_ARCH >= 7) +static int arm_arch = __ARM_ARCH; + +#define use_armv5_instructions (__ARM_ARCH >= 5 || arm_arch >= 5) +#define use_armv6_instructions (__ARM_ARCH >= 6 || arm_arch >= 6) +#define use_armv7_instructions (__ARM_ARCH >= 7 || arm_arch >= 7) #ifndef use_idiv_instructions bool use_idiv_instructions; @@ -2022,12 +2024,22 @@ static const TCGTargetOpDef arm_op_defs[] = { static void tcg_target_init(TCGContext *s) { -#if defined(CONFIG_GETAUXVAL) && !defined(use_idiv_instructions) +#if defined(CONFIG_GETAUXVAL) + /* Only probe for the platform and capabilities if we havn't already + determined maximum values at compile time. */ +# if !defined(use_idiv_instructions) { unsigned long hwcap = getauxval(AT_HWCAP); use_idiv_instructions = hwcap & (HWCAP_ARM_IDIVA | HWCAP_ARM_IDIVT); } -#endif +# endif + if (__ARM_ARCH < 7) { + const char *pl = (const char *)getauxval(AT_PLATFORM); + if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') { + arm_arch = pl[1] - '0'; + } + } +#endif /* GETAUXVAL */ tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff); tcg_regset_set32(tcg_target_call_clobber_regs, 0, -- 1.8.1.4