From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35214) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UrwhU-0006vK-Sr for qemu-devel@nongnu.org; Wed, 26 Jun 2013 16:52:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UrwhR-0000kR-8G for qemu-devel@nongnu.org; Wed, 26 Jun 2013 16:52:24 -0400 Received: from mail-pa0-x22a.google.com ([2607:f8b0:400e:c03::22a]:62568) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UrwhR-0000k5-1d for qemu-devel@nongnu.org; Wed, 26 Jun 2013 16:52:21 -0400 Received: by mail-pa0-f42.google.com with SMTP id rl6so75643pac.1 for ; Wed, 26 Jun 2013 13:52:20 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Wed, 26 Jun 2013 13:52:02 -0700 Message-Id: <1372279929-28836-3-git-send-email-rth@twiddle.net> In-Reply-To: <1372279929-28836-1-git-send-email-rth@twiddle.net> References: <1372279929-28836-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v2 2/9] tcg-arm: Don't implement rem List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: blauwirbel@gmail.com, claudio.fontana@huawei.com, aurelien@aurel32.net Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c | 14 -------------- tcg/arm/tcg-target.h | 3 +-- 2 files changed, 1 insertion(+), 16 deletions(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index 6be736b..8321f80 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -1926,18 +1926,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_divu_i32: tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]); break; - case INDEX_op_rem_i32: - tcg_out_sdiv(s, COND_AL, TCG_REG_TMP, args[1], args[2]); - tcg_out_mul32(s, COND_AL, TCG_REG_TMP, TCG_REG_TMP, args[2]); - tcg_out_dat_reg(s, COND_AL, ARITH_SUB, args[0], args[1], TCG_REG_TMP, - SHIFT_IMM_LSL(0)); - break; - case INDEX_op_remu_i32: - tcg_out_udiv(s, COND_AL, TCG_REG_TMP, args[1], args[2]); - tcg_out_mul32(s, COND_AL, TCG_REG_TMP, TCG_REG_TMP, args[2]); - tcg_out_dat_reg(s, COND_AL, ARITH_SUB, args[0], args[1], TCG_REG_TMP, - SHIFT_IMM_LSL(0)); - break; default: tcg_abort(); @@ -2043,9 +2031,7 @@ static const TCGTargetOpDef arm_op_defs[] = { #if TCG_TARGET_HAS_div_i32 { INDEX_op_div_i32, { "r", "r", "r" } }, - { INDEX_op_rem_i32, { "r", "r", "r" } }, { INDEX_op_divu_i32, { "r", "r", "r" } }, - { INDEX_op_remu_i32, { "r", "r", "r" } }, #endif { -1 }, diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 2c5b4e7..263ea03 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -76,11 +76,10 @@ typedef enum { #ifdef __ARM_ARCH_EXT_IDIV__ #define TCG_TARGET_HAS_div_i32 1 -#define TCG_TARGET_HAS_rem_i32 1 #else #define TCG_TARGET_HAS_div_i32 0 -#define TCG_TARGET_HAS_rem_i32 0 #endif +#define TCG_TARGET_HAS_rem_i32 0 extern bool tcg_target_deposit_valid(int ofs, int len); #define TCG_TARGET_deposit_i32_valid tcg_target_deposit_valid -- 1.8.1.4