From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: blauwirbel@gmail.com, claudio.fontana@huawei.com, aurelien@aurel32.net
Subject: [Qemu-devel] [PATCH v2 3/9] tcg-ppc: Don't implement rem
Date: Wed, 26 Jun 2013 13:52:03 -0700 [thread overview]
Message-ID: <1372279929-28836-4-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1372279929-28836-1-git-send-email-rth@twiddle.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/ppc/tcg-target.c | 14 --------------
tcg/ppc/tcg-target.h | 2 +-
2 files changed, 1 insertion(+), 15 deletions(-)
diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
index 29ca934..453ab6b 100644
--- a/tcg/ppc/tcg-target.c
+++ b/tcg/ppc/tcg-target.c
@@ -1671,18 +1671,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
break;
- case INDEX_op_rem_i32:
- tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
- tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
- tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
- break;
-
- case INDEX_op_remu_i32:
- tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
- tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
- tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
- break;
-
case INDEX_op_mulu2_i32:
if (args[0] == args[2] || args[0] == args[3]) {
tcg_out32 (s, MULLW | TAB (0, args[2], args[3]));
@@ -1992,8 +1980,6 @@ static const TCGTargetOpDef ppc_op_defs[] = {
{ INDEX_op_mul_i32, { "r", "r", "ri" } },
{ INDEX_op_div_i32, { "r", "r", "r" } },
{ INDEX_op_divu_i32, { "r", "r", "r" } },
- { INDEX_op_rem_i32, { "r", "r", "r" } },
- { INDEX_op_remu_i32, { "r", "r", "r" } },
{ INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
{ INDEX_op_sub_i32, { "r", "r", "ri" } },
{ INDEX_op_and_i32, { "r", "r", "ri" } },
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 01b880e..b42d97c 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -78,7 +78,7 @@ typedef enum {
/* optional instructions */
#define TCG_TARGET_HAS_div_i32 1
-#define TCG_TARGET_HAS_rem_i32 1
+#define TCG_TARGET_HAS_rem_i32 0
#define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_ext8s_i32 1
#define TCG_TARGET_HAS_ext16s_i32 1
--
1.8.1.4
next prev parent reply other threads:[~2013-06-26 20:52 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-06-26 20:52 [Qemu-devel] [PATCH v2 0/9] tcg: remainder and arm runtime detection Richard Henderson
2013-06-26 20:52 ` [Qemu-devel] [PATCH v2 1/9] tcg: Split rem requirement from div requirement Richard Henderson
2013-07-03 9:07 ` Claudio Fontana
2013-07-03 18:06 ` Richard Henderson
2013-06-26 20:52 ` [Qemu-devel] [PATCH v2 2/9] tcg-arm: Don't implement rem Richard Henderson
2013-06-26 20:52 ` Richard Henderson [this message]
2013-07-02 19:34 ` [Qemu-devel] [PATCH v2 3/9] tcg-ppc: " Andreas Färber
2013-06-26 20:52 ` [Qemu-devel] [PATCH v2 4/9] tcg-ppc64: " Richard Henderson
2013-07-02 19:34 ` Andreas Färber
2013-06-26 20:52 ` [Qemu-devel] [PATCH v2 5/9] tcg: Allow non-constant control macros Richard Henderson
2013-06-26 20:52 ` [Qemu-devel] [PATCH v2 6/9] tcg: Simplify logic using TCG_OPF_NOT_PRESENT Richard Henderson
2013-06-26 20:52 ` [Qemu-devel] [PATCH v2 7/9] tcg-arm: Make use of conditional availability of opcodes for divide Richard Henderson
2013-06-26 20:52 ` [Qemu-devel] [PATCH v2 8/9] tcg-arm: Simplify logic in detecting the ARM ISA in use Richard Henderson
2013-06-26 20:52 ` [Qemu-devel] [PATCH v2 9/9] tcg-arm: Use AT_PLATFORM to detect the host ISA Richard Henderson
2013-07-02 15:16 ` [Qemu-devel] [PATCH v2 0/9] tcg: remainder and arm runtime detection Richard Henderson
2013-07-02 19:17 ` Anthony Liguori
2013-07-02 19:42 ` Andreas Färber
2013-07-02 19:49 ` Peter Maydell
2013-07-02 20:25 ` Anthony Liguori
2013-07-02 21:02 ` Andreas Färber
2013-07-02 21:23 ` Peter Maydell
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