* [Qemu-devel] [PATCH 2/6] Added KVM Headers from KVM Tool
2013-06-28 12:11 [Qemu-devel] [PATCH 1/6] Added aarch64 configure support and default configuration Mian M. Hamayun
@ 2013-06-28 12:11 ` Mian M. Hamayun
2013-06-28 12:11 ` [Qemu-devel] [PATCH 3/6] Added Aarch64 CPU Initialization, Get and Put Registers Support Mian M. Hamayun
` (4 subsequent siblings)
5 siblings, 0 replies; 20+ messages in thread
From: Mian M. Hamayun @ 2013-06-28 12:11 UTC (permalink / raw)
To: qemu-devel; +Cc: tech, kvmarm, Mian M. Hamayun
From: "Mian M. Hamayun" <m.hamayun@virtualopensystems.com>
Signed-off-by: Mian M. Hamayun <m.hamayun@virtualopensystems.com>
---
| 168 ++++++++++++++++++++++++++++++++++++
| 1 +
2 files changed, 169 insertions(+)
create mode 100644 linux-headers/asm-arm64/kvm.h
create mode 100644 linux-headers/asm-arm64/kvm_para.h
--git a/linux-headers/asm-arm64/kvm.h b/linux-headers/asm-arm64/kvm.h
new file mode 100644
index 0000000..5031f42
--- /dev/null
+++ b/linux-headers/asm-arm64/kvm.h
@@ -0,0 +1,168 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * Derived from arch/arm/include/uapi/asm/kvm.h:
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ARM_KVM_H__
+#define __ARM_KVM_H__
+
+#define KVM_SPSR_EL1 0
+#define KVM_SPSR_SVC KVM_SPSR_EL1
+#define KVM_SPSR_ABT 1
+#define KVM_SPSR_UND 2
+#define KVM_SPSR_IRQ 3
+#define KVM_SPSR_FIQ 4
+#define KVM_NR_SPSR 5
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+#include <asm/ptrace.h>
+
+#define __KVM_HAVE_GUEST_DEBUG
+#define __KVM_HAVE_IRQ_LINE
+
+#define KVM_REG_SIZE(id) \
+ (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
+
+struct kvm_regs {
+ struct user_pt_regs regs; /* sp = sp_el0 */
+
+ __u64 sp_el1;
+ __u64 elr_el1;
+
+ __u64 spsr[KVM_NR_SPSR];
+
+ struct user_fpsimd_state fp_regs;
+};
+
+/* Supported Processor Types */
+#define KVM_ARM_TARGET_AEM_V8 0
+#define KVM_ARM_TARGET_FOUNDATION_V8 1
+#define KVM_ARM_TARGET_CORTEX_A57 2
+
+#define KVM_ARM_NUM_TARGETS 3
+
+/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
+#define KVM_ARM_DEVICE_TYPE_SHIFT 0
+#define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
+#define KVM_ARM_DEVICE_ID_SHIFT 16
+#define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT)
+
+/* Supported device IDs */
+#define KVM_ARM_DEVICE_VGIC_V2 0
+
+/* Supported VGIC address types */
+#define KVM_VGIC_V2_ADDR_TYPE_DIST 0
+#define KVM_VGIC_V2_ADDR_TYPE_CPU 1
+
+#define KVM_VGIC_V2_DIST_SIZE 0x1000
+#define KVM_VGIC_V2_CPU_SIZE 0x2000
+
+#define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */
+#define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */
+
+struct kvm_vcpu_init {
+ __u32 target;
+ __u32 features[7];
+};
+
+struct kvm_sregs {
+};
+
+struct kvm_fpu {
+};
+
+struct kvm_guest_debug_arch {
+};
+
+struct kvm_debug_exit_arch {
+};
+
+struct kvm_sync_regs {
+};
+
+struct kvm_arch_memory_slot {
+};
+
+/* If you need to interpret the index values, here is the key: */
+#define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000
+#define KVM_REG_ARM_COPROC_SHIFT 16
+
+/* Normal registers are mapped as coprocessor 16. */
+#define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
+#define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32))
+
+/* Some registers need more space to represent values. */
+#define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT)
+#define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00
+#define KVM_REG_ARM_DEMUX_ID_SHIFT 8
+#define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
+#define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF
+#define KVM_REG_ARM_DEMUX_VAL_SHIFT 0
+
+/* AArch64 system registers */
+#define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT)
+#define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000
+#define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14
+#define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800
+#define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11
+#define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780
+#define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7
+#define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078
+#define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3
+#define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007
+#define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0
+
+/* KVM_IRQ_LINE irq field index values */
+#define KVM_ARM_IRQ_TYPE_SHIFT 24
+#define KVM_ARM_IRQ_TYPE_MASK 0xff
+#define KVM_ARM_IRQ_VCPU_SHIFT 16
+#define KVM_ARM_IRQ_VCPU_MASK 0xff
+#define KVM_ARM_IRQ_NUM_SHIFT 0
+#define KVM_ARM_IRQ_NUM_MASK 0xffff
+
+/* irq_type field */
+#define KVM_ARM_IRQ_TYPE_CPU 0
+#define KVM_ARM_IRQ_TYPE_SPI 1
+#define KVM_ARM_IRQ_TYPE_PPI 2
+
+/* out-of-kernel GIC cpu interrupt injection irq_number field */
+#define KVM_ARM_IRQ_CPU_IRQ 0
+#define KVM_ARM_IRQ_CPU_FIQ 1
+
+/* Highest supported SPI, from VGIC_NR_IRQS */
+#define KVM_ARM_IRQ_GIC_MAX 127
+
+/* PSCI interface */
+#define KVM_PSCI_FN_BASE 0x95c1ba5e
+#define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n))
+
+#define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0)
+#define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1)
+#define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2)
+#define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3)
+
+#define KVM_PSCI_RET_SUCCESS 0
+#define KVM_PSCI_RET_NI ((unsigned long)-1)
+#define KVM_PSCI_RET_INVAL ((unsigned long)-2)
+#define KVM_PSCI_RET_DENIED ((unsigned long)-3)
+
+#endif
+
+#endif /* __ARM_KVM_H__ */
--git a/linux-headers/asm-arm64/kvm_para.h b/linux-headers/asm-arm64/kvm_para.h
new file mode 100644
index 0000000..14fab8f
--- /dev/null
+++ b/linux-headers/asm-arm64/kvm_para.h
@@ -0,0 +1 @@
+#include <asm-generic/kvm_para.h>
--
1.7.9.5
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 3/6] Added Aarch64 CPU Initialization, Get and Put Registers Support.
2013-06-28 12:11 [Qemu-devel] [PATCH 1/6] Added aarch64 configure support and default configuration Mian M. Hamayun
2013-06-28 12:11 ` [Qemu-devel] [PATCH 2/6] Added KVM Headers from KVM Tool Mian M. Hamayun
@ 2013-06-28 12:11 ` Mian M. Hamayun
2013-06-28 12:43 ` Alexander Graf
2013-06-29 19:17 ` Peter Maydell
2013-06-28 12:11 ` [Qemu-devel] [PATCH 4/6] Added the Versatile Express Machine Model for A57 Mian M. Hamayun
` (3 subsequent siblings)
5 siblings, 2 replies; 20+ messages in thread
From: Mian M. Hamayun @ 2013-06-28 12:11 UTC (permalink / raw)
To: qemu-devel; +Cc: tech, kvmarm, Mian M. Hamayun
From: "Mian M. Hamayun" <m.hamayun@virtualopensystems.com>
The init function tries to initialize with Foundation models first and on
failure retries initializing on Fast Models.
Get and Put Registers deal with the basic state of Aarch64 CPUs for the moment.
Signed-off-by: Mian M. Hamayun <m.hamayun@virtualopensystems.com>
---
| 1 +
target-arm/cpu.c | 8 +++
target-arm/cpu.h | 1 +
target-arm/kvm.c | 120 +++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 130 insertions(+)
--git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index c614070..4df5292 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -783,6 +783,7 @@ struct kvm_dirty_tlb {
#define KVM_REG_IA64 0x3000000000000000ULL
#define KVM_REG_ARM 0x4000000000000000ULL
#define KVM_REG_S390 0x5000000000000000ULL
+#define KVM_REG_ARM64 0x6000000000000000ULL
#define KVM_REG_SIZE_SHIFT 52
#define KVM_REG_SIZE_MASK 0x00f0000000000000ULL
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 496a59f..34eba77 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -601,6 +601,13 @@ static void cortex_a15_initfn(Object *obj)
define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
}
+static void cortex_a57_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ cpu->env.aarch64 = 1; /* We force 64-bit mode for guests */
+}
+
static void ti925t_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@@ -781,6 +788,7 @@ static const ARMCPUInfo arm_cpus[] = {
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
+ { .name = "cortex-a57", .initfn = cortex_a57_initfn },
{ .name = "ti925t", .initfn = ti925t_initfn },
{ .name = "sa1100", .initfn = sa1100_initfn },
{ .name = "sa1110", .initfn = sa1110_initfn },
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index cd42814..f1cae7f 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -410,6 +410,7 @@ enum arm_features {
ARM_FEATURE_V6,
ARM_FEATURE_V6K,
ARM_FEATURE_V7,
+ ARM_FEATURE_V8,
ARM_FEATURE_THUMB2,
ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */
ARM_FEATURE_VFP3,
diff --git a/target-arm/kvm.c b/target-arm/kvm.c
index 27dcab9..0125f16 100644
--- a/target-arm/kvm.c
+++ b/target-arm/kvm.c
@@ -23,6 +23,11 @@
#include "cpu.h"
#include "hw/arm/arm.h"
+#ifdef TARGET_AARCH64
+#define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
+ KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
+#endif
+
const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
KVM_CAP_LAST_INFO
};
@@ -41,6 +46,28 @@ unsigned long kvm_arch_vcpu_id(CPUState *cpu)
return cpu->cpu_index;
}
+#ifdef TARGET_AARCH64
+int kvm_arch_init_vcpu(CPUState *cs)
+{
+ struct kvm_vcpu_init init;
+ int ret;
+
+ /* Try initializing with Foundation Models */
+ init.target = KVM_ARM_TARGET_FOUNDATION_V8;
+ memset(init.features, 0, sizeof(init.features));
+ ret = kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init);
+ if (ret) {
+ /* Retry initializing with Fast Models */
+ init.target = KVM_ARM_TARGET_AEM_V8;
+ ret = kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init);
+ if (ret) {
+ return ret;
+ }
+ }
+
+ return ret;
+}
+#else
int kvm_arch_init_vcpu(CPUState *cs)
{
struct kvm_vcpu_init init;
@@ -67,6 +94,7 @@ int kvm_arch_init_vcpu(CPUState *cs)
}
return ret;
}
+#endif
/* We track all the KVM devices which need their memory addresses
* passing to the kernel in a list of these structures.
@@ -159,6 +187,7 @@ typedef struct Reg {
int offset;
} Reg;
+#ifndef TARGET_AARCH64
#define COREREG(KERNELNAME, QEMUFIELD) \
{ \
KVM_REG_ARM | KVM_REG_SIZE_U32 | \
@@ -239,7 +268,52 @@ static const Reg regs[] = {
VFPSYSREG(FPINST),
VFPSYSREG(FPINST2),
};
+#endif
+
+#ifdef TARGET_AARCH64
+int kvm_arch_put_registers(CPUState *cs, int level)
+{
+ struct kvm_one_reg reg;
+ int i;
+ int ret;
+
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+
+ for (i = 0; i < 31; i++) {
+ reg.id = AARCH64_CORE_REG(regs.regs[i]);
+ reg.addr = (uintptr_t)(env) + offsetof(CPUARMState, xregs[i]);
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
+ if (ret) {
+ return ret;
+ }
+ }
+
+ reg.id = AARCH64_CORE_REG(regs.sp);
+ reg.addr = (uintptr_t)(env) + offsetof(CPUARMState, xregs[31]);
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
+ if (ret) {
+ return ret;
+ }
+
+ reg.id = AARCH64_CORE_REG(regs.pstate);
+ reg.addr = (uintptr_t)(env) + offsetof(CPUARMState, pstate);
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
+ if (ret) {
+ return ret;
+ }
+ reg.id = AARCH64_CORE_REG(regs.pc);
+ reg.addr = (uintptr_t)(env) + offsetof(CPUARMState, pc);
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
+ if (ret) {
+ return ret;
+ }
+
+ /* TODO: Set Rest of Registers */
+ return ret;
+}
+#else
int kvm_arch_put_registers(CPUState *cs, int level)
{
ARMCPU *cpu = ARM_CPU(cs);
@@ -321,7 +395,52 @@ int kvm_arch_put_registers(CPUState *cs, int level)
return ret;
}
+#endif
+
+#ifdef TARGET_AARCH64
+int kvm_arch_get_registers(CPUState *cs)
+{
+ struct kvm_one_reg reg;
+ int i;
+ int ret;
+
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+
+ for (i = 0; i < 31; i++) {
+ reg.id = AARCH64_CORE_REG(regs.regs[i]);
+ reg.addr = (uintptr_t)(env) + offsetof(CPUARMState, xregs[i]);
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
+ if (ret) {
+ return ret;
+ }
+ }
+ reg.id = AARCH64_CORE_REG(regs.sp);
+ reg.addr = (uintptr_t)(env) + offsetof(CPUARMState, xregs[31]);
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
+ if (ret) {
+ return ret;
+ }
+
+ reg.id = AARCH64_CORE_REG(regs.pstate);
+ reg.addr = (uintptr_t)(env) + offsetof(CPUARMState, pstate);
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
+ if (ret) {
+ return ret;
+ }
+
+ reg.id = AARCH64_CORE_REG(regs.pc);
+ reg.addr = (uintptr_t)(env) + offsetof(CPUARMState, pc);
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
+ if (ret) {
+ return ret;
+ }
+
+ /* TODO: Set Rest of Registers */
+ return ret;
+}
+#else
int kvm_arch_get_registers(CPUState *cs)
{
ARMCPU *cpu = ARM_CPU(cs);
@@ -416,6 +535,7 @@ int kvm_arch_get_registers(CPUState *cs)
return 0;
}
+#endif
void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
{
--
1.7.9.5
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [Qemu-devel] [PATCH 3/6] Added Aarch64 CPU Initialization, Get and Put Registers Support.
2013-06-28 12:11 ` [Qemu-devel] [PATCH 3/6] Added Aarch64 CPU Initialization, Get and Put Registers Support Mian M. Hamayun
@ 2013-06-28 12:43 ` Alexander Graf
2013-06-29 17:48 ` Mian M. Hamayun
2013-06-29 19:17 ` Peter Maydell
1 sibling, 1 reply; 20+ messages in thread
From: Alexander Graf @ 2013-06-28 12:43 UTC (permalink / raw)
To: Mian M. Hamayun; +Cc: tech, qemu-devel, kvmarm
On 28.06.2013, at 14:11, Mian M. Hamayun wrote:
> From: "Mian M. Hamayun" <m.hamayun@virtualopensystems.com>
>
> The init function tries to initialize with Foundation models first and on
> failure retries initializing on Fast Models.
>
> Get and Put Registers deal with the basic state of Aarch64 CPUs for the moment.
>
> Signed-off-by: Mian M. Hamayun <m.hamayun@virtualopensystems.com>
> ---
> linux-headers/linux/kvm.h | 1 +
> target-arm/cpu.c | 8 +++
> target-arm/cpu.h | 1 +
> target-arm/kvm.c | 120 +++++++++++++++++++++++++++++++++++++++++++++
> 4 files changed, 130 insertions(+)
>
> diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
> index c614070..4df5292 100644
> --- a/linux-headers/linux/kvm.h
> +++ b/linux-headers/linux/kvm.h
> @@ -783,6 +783,7 @@ struct kvm_dirty_tlb {
> #define KVM_REG_IA64 0x3000000000000000ULL
> #define KVM_REG_ARM 0x4000000000000000ULL
> #define KVM_REG_S390 0x5000000000000000ULL
> +#define KVM_REG_ARM64 0x6000000000000000ULL
>
> #define KVM_REG_SIZE_SHIFT 52
> #define KVM_REG_SIZE_MASK 0x00f0000000000000ULL
This should be part of your header update patch.
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index 496a59f..34eba77 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -601,6 +601,13 @@ static void cortex_a15_initfn(Object *obj)
> define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
> }
>
> +static void cortex_a57_initfn(Object *obj)
> +{
> + ARMCPU *cpu = ARM_CPU(obj);
> + set_feature(&cpu->env, ARM_FEATURE_V8);
> + cpu->env.aarch64 = 1; /* We force 64-bit mode for guests */
> +}
> +
> static void ti925t_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> @@ -781,6 +788,7 @@ static const ARMCPUInfo arm_cpus[] = {
> { .name = "cortex-a8", .initfn = cortex_a8_initfn },
> { .name = "cortex-a9", .initfn = cortex_a9_initfn },
> { .name = "cortex-a15", .initfn = cortex_a15_initfn },
> + { .name = "cortex-a57", .initfn = cortex_a57_initfn },
> { .name = "ti925t", .initfn = ti925t_initfn },
> { .name = "sa1100", .initfn = sa1100_initfn },
> { .name = "sa1110", .initfn = sa1110_initfn },
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index cd42814..f1cae7f 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -410,6 +410,7 @@ enum arm_features {
> ARM_FEATURE_V6,
> ARM_FEATURE_V6K,
> ARM_FEATURE_V7,
> + ARM_FEATURE_V8,
> ARM_FEATURE_THUMB2,
> ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */
> ARM_FEATURE_VFP3,
> diff --git a/target-arm/kvm.c b/target-arm/kvm.c
> index 27dcab9..0125f16 100644
> --- a/target-arm/kvm.c
> +++ b/target-arm/kvm.c
> @@ -23,6 +23,11 @@
> #include "cpu.h"
> #include "hw/arm/arm.h"
>
> +#ifdef TARGET_AARCH64
> +#define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
> + KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
> +#endif
> +
> const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
> KVM_CAP_LAST_INFO
> };
> @@ -41,6 +46,28 @@ unsigned long kvm_arch_vcpu_id(CPUState *cpu)
> return cpu->cpu_index;
> }
>
> +#ifdef TARGET_AARCH64
> +int kvm_arch_init_vcpu(CPUState *cs)
> +{
> + struct kvm_vcpu_init init;
> + int ret;
> +
> + /* Try initializing with Foundation Models */
> + init.target = KVM_ARM_TARGET_FOUNDATION_V8;
> + memset(init.features, 0, sizeof(init.features));
> + ret = kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init);
> + if (ret) {
> + /* Retry initializing with Fast Models */
> + init.target = KVM_ARM_TARGET_AEM_V8;
> + ret = kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init);
Not sure I understand this part. Do we have different CPU types for the different models? If so, they'd be different -cpu parameters, with -cpu host picking the same as the host's.
> + if (ret) {
> + return ret;
> + }
> + }
> +
> + return ret;
> +}
> +#else
> int kvm_arch_init_vcpu(CPUState *cs)
> {
> struct kvm_vcpu_init init;
> @@ -67,6 +94,7 @@ int kvm_arch_init_vcpu(CPUState *cs)
> }
> return ret;
> }
> +#endif
>
> /* We track all the KVM devices which need their memory addresses
> * passing to the kernel in a list of these structures.
> @@ -159,6 +187,7 @@ typedef struct Reg {
> int offset;
> } Reg;
>
> +#ifndef TARGET_AARCH64
> #define COREREG(KERNELNAME, QEMUFIELD) \
> { \
> KVM_REG_ARM | KVM_REG_SIZE_U32 | \
> @@ -239,7 +268,52 @@ static const Reg regs[] = {
> VFPSYSREG(FPINST),
> VFPSYSREG(FPINST2),
> };
> +#endif
> +
> +#ifdef TARGET_AARCH64
> +int kvm_arch_put_registers(CPUState *cs, int level)
How does the register transaction interface look like for aarch64 kvm? Are aarch32 registers mapped onto aarch64 ones or are they a separate set of registers? If they're a separate set, just add the aarch64 register sync to the aarch32 one.
> +{
> + struct kvm_one_reg reg;
> + int i;
> + int ret;
> +
> + ARMCPU *cpu = ARM_CPU(cs);
> + CPUARMState *env = &cpu->env;
> +
> + for (i = 0; i < 31; i++) {
s/31/ARRAY_SIZE(...)/
> + reg.id = AARCH64_CORE_REG(regs.regs[i]);
> + reg.addr = (uintptr_t)(env) + offsetof(CPUARMState, xregs[i]);
reg.addr = (uintptr_t)&env->xregs[i];
Same below.
Alex
> + ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
> + if (ret) {
> + return ret;
> + }
> + }
> +
> + reg.id = AARCH64_CORE_REG(regs.sp);
> + reg.addr = (uintptr_t)(env) + offsetof(CPUARMState, xregs[31]);
> + ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
> + if (ret) {
> + return ret;
> + }
> +
> + reg.id = AARCH64_CORE_REG(regs.pstate);
> + reg.addr = (uintptr_t)(env) + offsetof(CPUARMState, pstate);
> + ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
> + if (ret) {
> + return ret;
> + }
>
> + reg.id = AARCH64_CORE_REG(regs.pc);
> + reg.addr = (uintptr_t)(env) + offsetof(CPUARMState, pc);
> + ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
> + if (ret) {
> + return ret;
> + }
> +
> + /* TODO: Set Rest of Registers */
> + return ret;
> +}
> +#else
> int kvm_arch_put_registers(CPUState *cs, int level)
> {
> ARMCPU *cpu = ARM_CPU(cs);
> @@ -321,7 +395,52 @@ int kvm_arch_put_registers(CPUState *cs, int level)
>
> return ret;
> }
> +#endif
> +
> +#ifdef TARGET_AARCH64
> +int kvm_arch_get_registers(CPUState *cs)
> +{
> + struct kvm_one_reg reg;
> + int i;
> + int ret;
> +
> + ARMCPU *cpu = ARM_CPU(cs);
> + CPUARMState *env = &cpu->env;
> +
> + for (i = 0; i < 31; i++) {
> + reg.id = AARCH64_CORE_REG(regs.regs[i]);
> + reg.addr = (uintptr_t)(env) + offsetof(CPUARMState, xregs[i]);
> + ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
> + if (ret) {
> + return ret;
> + }
> + }
>
> + reg.id = AARCH64_CORE_REG(regs.sp);
> + reg.addr = (uintptr_t)(env) + offsetof(CPUARMState, xregs[31]);
> + ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
> + if (ret) {
> + return ret;
> + }
> +
> + reg.id = AARCH64_CORE_REG(regs.pstate);
> + reg.addr = (uintptr_t)(env) + offsetof(CPUARMState, pstate);
> + ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
> + if (ret) {
> + return ret;
> + }
> +
> + reg.id = AARCH64_CORE_REG(regs.pc);
> + reg.addr = (uintptr_t)(env) + offsetof(CPUARMState, pc);
> + ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
> + if (ret) {
> + return ret;
> + }
> +
> + /* TODO: Set Rest of Registers */
> + return ret;
> +}
> +#else
> int kvm_arch_get_registers(CPUState *cs)
> {
> ARMCPU *cpu = ARM_CPU(cs);
> @@ -416,6 +535,7 @@ int kvm_arch_get_registers(CPUState *cs)
>
> return 0;
> }
> +#endif
>
> void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
> {
> --
> 1.7.9.5
>
> _______________________________________________
> kvmarm mailing list
> kvmarm@lists.cs.columbia.edu
> https://lists.cs.columbia.edu/cucslists/listinfo/kvmarm
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [Qemu-devel] [PATCH 3/6] Added Aarch64 CPU Initialization, Get and Put Registers Support.
2013-06-28 12:43 ` Alexander Graf
@ 2013-06-29 17:48 ` Mian M. Hamayun
2013-06-29 18:05 ` Alexander Graf
0 siblings, 1 reply; 20+ messages in thread
From: Mian M. Hamayun @ 2013-06-29 17:48 UTC (permalink / raw)
To: Alexander Graf; +Cc: tech, qemu-devel, kvmarm
On 06/28/2013 02:43 PM, Alexander Graf wrote:
> On 28.06.2013, at 14:11, Mian M. Hamayun wrote:
>
>> diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
>> index c614070..4df5292 100644
>> --- a/linux-headers/linux/kvm.h
>> +++ b/linux-headers/linux/kvm.h
>> @@ -783,6 +783,7 @@ struct kvm_dirty_tlb {
>> #define KVM_REG_IA64 0x3000000000000000ULL
>> #define KVM_REG_ARM 0x4000000000000000ULL
>> #define KVM_REG_S390 0x5000000000000000ULL
>> +#define KVM_REG_ARM64 0x6000000000000000ULL
>>
>> #define KVM_REG_SIZE_SHIFT 52
>> #define KVM_REG_SIZE_MASK 0x00f0000000000000ULL
> This should be part of your header update patch.
Just to make sure that we understand it correctly, do you mean that this
macro definition should be moved to the arm64 specific header that we
include in another patch series ? or keep this change in the same file
and do it along with the header inclusion in a single patch ?
>> +#ifdef TARGET_AARCH64
>> +int kvm_arch_init_vcpu(CPUState *cs)
>> +{
>> + struct kvm_vcpu_init init;
>> + int ret;
>> +
>> + /* Try initializing with Foundation Models */
>> + init.target = KVM_ARM_TARGET_FOUNDATION_V8;
>> + memset(init.features, 0, sizeof(init.features));
>> + ret = kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init);
>> + if (ret) {
>> + /* Retry initializing with Fast Models */
>> + init.target = KVM_ARM_TARGET_AEM_V8;
>> + ret = kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init);
> Not sure I understand this part. Do we have different CPU types for the different models? If so, they'd be different -cpu parameters, with -cpu host picking the same as the host's.
KVM tool does a very similar thing, using a loop and tries to initialize
supported processors types and gets done when it succeeds with anyone of
them. We could include a similar implementation in the next revision.
>> +{
>> + struct kvm_one_reg reg;
>> + int i;
>> + int ret;
>> +
>> + ARMCPU *cpu = ARM_CPU(cs);
>> + CPUARMState *env = &cpu->env;
>> +
>> + for (i = 0; i < 31; i++) {
> s/31/ARRAY_SIZE(...)/
Agreed, we should avoid hard-coding as much as possible.
>> + reg.id = AARCH64_CORE_REG(regs.regs[i]);
>> + reg.addr = (uintptr_t)(env) + offsetof(CPUARMState, xregs[i]);
> reg.addr = (uintptr_t)&env->xregs[i];
Our implementation was influenced by the existing
kvm_arch_get_registers() implementation for the A15 CPU, with slight
differences. Anyways, we will include the proposed change in the next
revision.
--
Hamayun
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [Qemu-devel] [PATCH 3/6] Added Aarch64 CPU Initialization, Get and Put Registers Support.
2013-06-29 17:48 ` Mian M. Hamayun
@ 2013-06-29 18:05 ` Alexander Graf
0 siblings, 0 replies; 20+ messages in thread
From: Alexander Graf @ 2013-06-29 18:05 UTC (permalink / raw)
To: m.hamayun; +Cc: tech, qemu-devel, kvmarm
On 29.06.2013, at 19:48, Mian M. Hamayun wrote:
>
> On 06/28/2013 02:43 PM, Alexander Graf wrote:
>> On 28.06.2013, at 14:11, Mian M. Hamayun wrote:
>>
>>> diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
>>> index c614070..4df5292 100644
>>> --- a/linux-headers/linux/kvm.h
>>> +++ b/linux-headers/linux/kvm.h
>>> @@ -783,6 +783,7 @@ struct kvm_dirty_tlb {
>>> #define KVM_REG_IA64 0x3000000000000000ULL
>>> #define KVM_REG_ARM 0x4000000000000000ULL
>>> #define KVM_REG_S390 0x5000000000000000ULL
>>> +#define KVM_REG_ARM64 0x6000000000000000ULL
>>>
>>> #define KVM_REG_SIZE_SHIFT 52
>>> #define KVM_REG_SIZE_MASK 0x00f0000000000000ULL
>> This should be part of your header update patch.
> Just to make sure that we understand it correctly, do you mean that this macro definition should be moved to the arm64 specific header that we include in another patch series ? or keep this change in the same file and do it along with the header inclusion in a single patch ?
I'm saying you should generate the Linux header update from an upstream branch that includes this change.
>>> +#ifdef TARGET_AARCH64
>>> +int kvm_arch_init_vcpu(CPUState *cs)
>>> +{
>>> + struct kvm_vcpu_init init;
>>> + int ret;
>>> +
>>> + /* Try initializing with Foundation Models */
>>> + init.target = KVM_ARM_TARGET_FOUNDATION_V8;
>>> + memset(init.features, 0, sizeof(init.features));
>>> + ret = kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init);
>>> + if (ret) {
>>> + /* Retry initializing with Fast Models */
>>> + init.target = KVM_ARM_TARGET_AEM_V8;
>>> + ret = kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init);
>> Not sure I understand this part. Do we have different CPU types for the different models? If so, they'd be different -cpu parameters, with -cpu host picking the same as the host's.
> KVM tool does a very similar thing, using a loop and tries to initialize supported processors types and gets done when it succeeds with anyone of them. We could include a similar implementation in the next revision.
Is there no way to evaluate what we're running on so that we can expose the same thing to the guest? It's what -cpu host does usually. Taking one by trial-and-error breaks cross-virtualization.
Alex
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [PATCH 3/6] Added Aarch64 CPU Initialization, Get and Put Registers Support.
2013-06-28 12:11 ` [Qemu-devel] [PATCH 3/6] Added Aarch64 CPU Initialization, Get and Put Registers Support Mian M. Hamayun
2013-06-28 12:43 ` Alexander Graf
@ 2013-06-29 19:17 ` Peter Maydell
2013-07-01 17:54 ` Alexander Spyridakis
1 sibling, 1 reply; 20+ messages in thread
From: Peter Maydell @ 2013-06-29 19:17 UTC (permalink / raw)
To: Mian M. Hamayun; +Cc: tech, qemu-devel, kvmarm
On 28 June 2013 13:11, Mian M. Hamayun <m.hamayun@virtualopensystems.com> wrote:
> From: "Mian M. Hamayun" <m.hamayun@virtualopensystems.com>
>
> The init function tries to initialize with Foundation models first and on
> failure retries initializing on Fast Models.
>
> Get and Put Registers deal with the basic state of Aarch64 CPUs for the moment.
>
> Signed-off-by: Mian M. Hamayun <m.hamayun@virtualopensystems.com>
> ---
> linux-headers/linux/kvm.h | 1 +
> target-arm/cpu.c | 8 +++
> target-arm/cpu.h | 1 +
> target-arm/kvm.c | 120 +++++++++++++++++++++++++++++++++++++++++++++
> 4 files changed, 130 insertions(+)
>
> diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
> index c614070..4df5292 100644
> --- a/linux-headers/linux/kvm.h
> +++ b/linux-headers/linux/kvm.h
> @@ -783,6 +783,7 @@ struct kvm_dirty_tlb {
> #define KVM_REG_IA64 0x3000000000000000ULL
> #define KVM_REG_ARM 0x4000000000000000ULL
> #define KVM_REG_S390 0x5000000000000000ULL
> +#define KVM_REG_ARM64 0x6000000000000000ULL
>
> #define KVM_REG_SIZE_SHIFT 52
> #define KVM_REG_SIZE_MASK 0x00f0000000000000ULL
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index 496a59f..34eba77 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -601,6 +601,13 @@ static void cortex_a15_initfn(Object *obj)
> define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
> }
>
> +static void cortex_a57_initfn(Object *obj)
> +{
> + ARMCPU *cpu = ARM_CPU(obj);
> + set_feature(&cpu->env, ARM_FEATURE_V8);
> + cpu->env.aarch64 = 1; /* We force 64-bit mode for guests */
This is definitely in the wrong place. cpu reset for
64 bit CPUs should start them off in AArch64.
> +}
> +
> static void ti925t_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> @@ -781,6 +788,7 @@ static const ARMCPUInfo arm_cpus[] = {
> { .name = "cortex-a8", .initfn = cortex_a8_initfn },
> { .name = "cortex-a9", .initfn = cortex_a9_initfn },
> { .name = "cortex-a15", .initfn = cortex_a15_initfn },
> + { .name = "cortex-a57", .initfn = cortex_a57_initfn },
> { .name = "ti925t", .initfn = ti925t_initfn },
> { .name = "sa1100", .initfn = sa1100_initfn },
> { .name = "sa1110", .initfn = sa1110_initfn },
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index cd42814..f1cae7f 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -410,6 +410,7 @@ enum arm_features {
> ARM_FEATURE_V6,
> ARM_FEATURE_V6K,
> ARM_FEATURE_V7,
> + ARM_FEATURE_V8,
> ARM_FEATURE_THUMB2,
> ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */
> ARM_FEATURE_VFP3,
> diff --git a/target-arm/kvm.c b/target-arm/kvm.c
> index 27dcab9..0125f16 100644
> --- a/target-arm/kvm.c
> +++ b/target-arm/kvm.c
> @@ -23,6 +23,11 @@
> #include "cpu.h"
> #include "hw/arm/arm.h"
>
> +#ifdef TARGET_AARCH64
> +#define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
> + KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
> +#endif
> +
> const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
> KVM_CAP_LAST_INFO
> };
> @@ -41,6 +46,28 @@ unsigned long kvm_arch_vcpu_id(CPUState *cpu)
> return cpu->cpu_index;
> }
>
> +#ifdef TARGET_AARCH64
> +int kvm_arch_init_vcpu(CPUState *cs)
> +{
> + struct kvm_vcpu_init init;
> + int ret;
> +
> + /* Try initializing with Foundation Models */
> + init.target = KVM_ARM_TARGET_FOUNDATION_V8;
> + memset(init.features, 0, sizeof(init.features));
> + ret = kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init);
> + if (ret) {
> + /* Retry initializing with Fast Models */
> + init.target = KVM_ARM_TARGET_AEM_V8;
If we're emulating an A57 we should be asking KVM for an A57
guest. If we're asking KVM for "a CPU like the one in
the Foundation model" we need to support that via -cpu $something.
But I'm a bit dubious about that anyway -- you need to provide
a good justification for why KVM/QEMU should be emulating
emulators and not hardware.
-- PMM
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [Qemu-devel] [PATCH 3/6] Added Aarch64 CPU Initialization, Get and Put Registers Support.
2013-06-29 19:17 ` Peter Maydell
@ 2013-07-01 17:54 ` Alexander Spyridakis
0 siblings, 0 replies; 20+ messages in thread
From: Alexander Spyridakis @ 2013-07-01 17:54 UTC (permalink / raw)
To: Peter Maydell; +Cc: tech, qemu-devel, Mian M. Hamayun, kvmarm
On 29 June 2013 21:17, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> > +#ifdef TARGET_AARCH64
> > +int kvm_arch_init_vcpu(CPUState *cs)
> > +{
> > + struct kvm_vcpu_init init;
> > + int ret;
> > +
> > + /* Try initializing with Foundation Models */
> > + init.target = KVM_ARM_TARGET_FOUNDATION_V8;
> > + memset(init.features, 0, sizeof(init.features));
> > + ret = kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init);
> > + if (ret) {
> > + /* Retry initializing with Fast Models */
> > + init.target = KVM_ARM_TARGET_AEM_V8;
>
> If we're emulating an A57 we should be asking KVM for an A57
> guest. If we're asking KVM for "a CPU like the one in
> the Foundation model" we need to support that via -cpu $something.
Wouldn't that be an overkill at this early stage? There is no target
to test KVM_ARM_TARGET_CORTEX_A57 so we opted for the other two tested
cases.
> But I'm a bit dubious about that anyway -- you need to provide
> a good justification for why KVM/QEMU should be emulating
> emulators and not hardware.
Mainly because there is no real hardware yet. This patch series was
meant to enable basic working support of KVM in AArch64 on what is
available and open discussion on how to proceed from there. Also,
given that fact that kvmtool uses the same approach it was the most
obvious way at the time to handle it.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH 4/6] Added the Versatile Express Machine Model for A57
2013-06-28 12:11 [Qemu-devel] [PATCH 1/6] Added aarch64 configure support and default configuration Mian M. Hamayun
2013-06-28 12:11 ` [Qemu-devel] [PATCH 2/6] Added KVM Headers from KVM Tool Mian M. Hamayun
2013-06-28 12:11 ` [Qemu-devel] [PATCH 3/6] Added Aarch64 CPU Initialization, Get and Put Registers Support Mian M. Hamayun
@ 2013-06-28 12:11 ` Mian M. Hamayun
2013-06-29 19:21 ` Peter Maydell
2013-06-28 12:11 ` [Qemu-devel] [PATCH 5/6] Added Boot Support for Aarch64 Processor Mian M. Hamayun
` (2 subsequent siblings)
5 siblings, 1 reply; 20+ messages in thread
From: Mian M. Hamayun @ 2013-06-28 12:11 UTC (permalink / raw)
To: qemu-devel; +Cc: tech, kvmarm, Mian M. Hamayun
From: "Mian M. Hamayun" <m.hamayun@virtualopensystems.com>
The vexpress model for A57 is based on the A15 machine model with a few
changes in the daughterboard initialization (using a subset of A15
functionality). The A57 daughterboard init also shares the A15MPCore
private memory region with A15 daughterboard init function.
Signed-off-by: Mian M. Hamayun <m.hamayun@virtualopensystems.com>
---
hw/arm/vexpress.c | 91 +++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 91 insertions(+)
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index a077c62..e8070f3 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -393,6 +393,74 @@ static const VEDBoardInfo a15_daughterboard = {
.init = a15_daughterboard_init,
};
+static void a57_daughterboard_init(const VEDBoardInfo *daughterboard,
+ ram_addr_t ram_size,
+ const char *cpu_model,
+ qemu_irq *pic)
+{
+ int n;
+ MemoryRegion *sysmem = get_system_memory();
+ MemoryRegion *ram = g_new(MemoryRegion, 1);
+ qemu_irq cpu_irq[4];
+ DeviceState *dev;
+ SysBusDevice *busdev;
+
+ if (!cpu_model) {
+ cpu_model = "cortex-a57";
+ }
+
+ for (n = 0; n < smp_cpus; n++) {
+ ARMCPU *cpu;
+ qemu_irq *irqp;
+
+ cpu = cpu_arm_init(cpu_model);
+ if (!cpu) {
+ fprintf(stderr, "Unable to find CPU definition\n");
+ exit(1);
+ }
+ irqp = arm_pic_init_cpu(cpu);
+ cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
+ }
+
+ {
+ /* We have to use a separate 64 bit variable here to avoid the gcc
+ * "comparison is always false due to limited range of data type"
+ * warning if we are on a host where ram_addr_t is 32 bits.
+ */
+ uint64_t rsz = ram_size;
+ if (rsz > (30ULL * 1024 * 1024 * 1024)) {
+ fprintf(stderr, "vexpress-a57: cannot model more than 30GB RAM\n");
+ exit(1);
+ }
+ }
+
+ memory_region_init_ram(ram, "vexpress.lowmem", ram_size);
+ vmstate_register_ram_global(ram);
+ /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */
+ memory_region_add_subregion(sysmem, 0x80000000, ram);
+
+ /* 0x2c000000 A15MPCore private memory region (GIC) */
+ dev = qdev_create(NULL, "a15mpcore_priv");
+ qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
+ qdev_init_nofail(dev);
+ busdev = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(busdev, 0, 0x2c000000);
+ for (n = 0; n < smp_cpus; n++) {
+ sysbus_connect_irq(busdev, n, cpu_irq[n]);
+ }
+ /* Interrupts [42:0] are from the motherboard;
+ * [47:43] are reserved; [63:48] are daughterboard
+ * peripherals. Note that some documentation numbers
+ * external interrupts starting from 32 (because there
+ * are internal interrupts 0..31).
+ */
+ for (n = 0; n < 64; n++) {
+ pic[n] = qdev_get_gpio_in(dev, n);
+ }
+
+ /* A57 daughterboard peripherals: not modeled */
+}
+
static void vexpress_common_init(const VEDBoardInfo *daughterboard,
QEMUMachineInitArgs *args)
{
@@ -522,6 +590,14 @@ static void vexpress_common_init(const VEDBoardInfo *daughterboard,
arm_load_kernel(arm_env_get_cpu(first_cpu), &vexpress_binfo);
}
+static const VEDBoardInfo a57_daughterboard = {
+ .motherboard_map = motherboard_aseries_map,
+ .loader_start = 0x80000000,
+ .gic_cpu_if_addr = 0x2c002000,
+ .proc_id = 0x14000237,
+ .init = a57_daughterboard_init,
+};
+
static void vexpress_a9_init(QEMUMachineInitArgs *args)
{
vexpress_common_init(&a9_daughterboard, args);
@@ -532,6 +608,11 @@ static void vexpress_a15_init(QEMUMachineInitArgs *args)
vexpress_common_init(&a15_daughterboard, args);
}
+static void vexpress_a57_init(QEMUMachineInitArgs *args)
+{
+ vexpress_common_init(&a57_daughterboard, args);
+}
+
static QEMUMachine vexpress_a9_machine = {
.name = "vexpress-a9",
.desc = "ARM Versatile Express for Cortex-A9",
@@ -550,10 +631,20 @@ static QEMUMachine vexpress_a15_machine = {
DEFAULT_MACHINE_OPTIONS,
};
+static QEMUMachine vexpress_a57_machine = {
+ .name = "vexpress-a57",
+ .desc = "ARM Versatile Express for Cortex-A57",
+ .init = vexpress_a57_init,
+ .block_default_type = IF_SCSI,
+ .max_cpus = 4,
+ DEFAULT_MACHINE_OPTIONS,
+};
+
static void vexpress_machine_init(void)
{
qemu_register_machine(&vexpress_a9_machine);
qemu_register_machine(&vexpress_a15_machine);
+ qemu_register_machine(&vexpress_a57_machine);
}
machine_init(vexpress_machine_init);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [Qemu-devel] [PATCH 4/6] Added the Versatile Express Machine Model for A57
2013-06-28 12:11 ` [Qemu-devel] [PATCH 4/6] Added the Versatile Express Machine Model for A57 Mian M. Hamayun
@ 2013-06-29 19:21 ` Peter Maydell
2013-07-01 18:06 ` Alexander Spyridakis
0 siblings, 1 reply; 20+ messages in thread
From: Peter Maydell @ 2013-06-29 19:21 UTC (permalink / raw)
To: Mian M. Hamayun; +Cc: tech, qemu-devel, kvmarm
On 28 June 2013 13:11, Mian M. Hamayun <m.hamayun@virtualopensystems.com> wrote:
> From: "Mian M. Hamayun" <m.hamayun@virtualopensystems.com>
>
> The vexpress model for A57 is based on the A15 machine model with a few
> changes in the daughterboard initialization (using a subset of A15
> functionality). The A57 daughterboard init also shares the A15MPCore
> private memory region with A15 daughterboard init function.
So, which documentation or TRM or hardware are you basing this
definition of an A57 Versatile Express daughterboard on?
-- PMM
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [PATCH 4/6] Added the Versatile Express Machine Model for A57
2013-06-29 19:21 ` Peter Maydell
@ 2013-07-01 18:06 ` Alexander Spyridakis
2013-07-01 19:08 ` Peter Maydell
0 siblings, 1 reply; 20+ messages in thread
From: Alexander Spyridakis @ 2013-07-01 18:06 UTC (permalink / raw)
To: Peter Maydell; +Cc: tech, qemu-devel, Mian M. Hamayun, kvmarm
On 29 June 2013 21:21, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 28 June 2013 13:11, Mian M. Hamayun <m.hamayun@virtualopensystems.com> wrote:
> > From: "Mian M. Hamayun" <m.hamayun@virtualopensystems.com>
> >
> > The vexpress model for A57 is based on the A15 machine model with a few
> > changes in the daughterboard initialization (using a subset of A15
> > functionality). The A57 daughterboard init also shares the A15MPCore
> > private memory region with A15 daughterboard init function.
>
> So, which documentation or TRM or hardware are you basing this
> definition of an A57 Versatile Express daughterboard on?
Currently there is no existing hardware that I am aware of, or a
public TRM describing it. On existing ARMv8 models the peripherals
used and the platform memory map seems to be identical with the
previous iteration. Based on that, the same approach was followed to
have a working setup, on which to base further development when
another target is available.
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [PATCH 4/6] Added the Versatile Express Machine Model for A57
2013-07-01 18:06 ` Alexander Spyridakis
@ 2013-07-01 19:08 ` Peter Maydell
0 siblings, 0 replies; 20+ messages in thread
From: Peter Maydell @ 2013-07-01 19:08 UTC (permalink / raw)
To: Alexander Spyridakis; +Cc: tech, qemu-devel, Mian M. Hamayun, kvmarm
On 1 July 2013 19:06, Alexander Spyridakis
<a.spyridakis@virtualopensystems.com> wrote:
> On 29 June 2013 21:21, Peter Maydell <peter.maydell@linaro.org> wrote:
>> So, which documentation or TRM or hardware are you basing this
>> definition of an A57 Versatile Express daughterboard on?
>
> Currently there is no existing hardware that I am aware of, or a
> public TRM describing it.
Then you can't put a board model into QEMU that claims to be
a vexpress-a57. What you want is mach-virt (see John Rigby's
patchset).
thanks
-- PMM
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH 5/6] Added Boot Support for Aarch64 Processor.
2013-06-28 12:11 [Qemu-devel] [PATCH 1/6] Added aarch64 configure support and default configuration Mian M. Hamayun
` (2 preceding siblings ...)
2013-06-28 12:11 ` [Qemu-devel] [PATCH 4/6] Added the Versatile Express Machine Model for A57 Mian M. Hamayun
@ 2013-06-28 12:11 ` Mian M. Hamayun
2013-06-28 12:11 ` [Qemu-devel] [PATCH 6/6] Added SMP for Aarch64 Processors Mian M. Hamayun
2013-06-29 19:20 ` [Qemu-devel] [PATCH 1/6] Added aarch64 configure support and default configuration Peter Maydell
5 siblings, 0 replies; 20+ messages in thread
From: Mian M. Hamayun @ 2013-06-28 12:11 UTC (permalink / raw)
To: qemu-devel; +Cc: tech, kvmarm, Mian M. Hamayun
From: "Mian M. Hamayun" <m.hamayun@virtualopensystems.com>
This version supports booting of a single Aarch64 CPU by setting appropriate
registers. The bootloader includes placehoders for Board-ID that are used to
implementing uniform indexing across different bootloaders.
The same macro names are used with different values when compiling for different
processors.
Signed-off-by: Mian M. Hamayun <m.hamayun@virtualopensystems.com>
---
hw/arm/boot.c | 45 +++++++++++++++++++++++++++++++++++++++------
1 file changed, 39 insertions(+), 6 deletions(-)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index defcf15..94e628b 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -18,7 +18,33 @@
#include "qemu/config-file.h"
#define KERNEL_ARGS_ADDR 0x100
-#define KERNEL_LOAD_ADDR 0x00010000
+
+#ifdef TARGET_AARCH64
+#define KERNEL_LOAD_ADDR 0x00080000
+#define KERNEL_ARGS_INDEX 6
+#define KERNEL_ENTRY_INDEX 8
+#define KERNEL_BOARDID_INDEX 10
+
+static uint32_t bootloader[] = {
+ 0x580000c0, /* ldr x0, 18 <_start+0x18> */
+ 0xaa1f03e1, /* mov x1, xzr */
+ 0xaa1f03e2, /* mov x2, xzr */
+ 0xaa1f03e3, /* mov x3, xzr */
+ 0x58000084, /* ldr x4, 20 <_start+0x20> */
+ 0xd61f0080, /* br x4 */
+ 0x00000000, /* .word @DTB Lower 32-bits */
+ 0x00000000, /* .word @DTB Higher 32-bits */
+ 0x00000000, /* .word @Kernel Entry Lower 32-bits */
+ 0x00000000, /* .word @Kernel Entry Higher 32-bits */
+ 0x00000000, /* .word @Board ID Lower 32-bits -- Placeholder */
+ 0x00000000 /* .word @Board ID Higher 32-bits -- Placeholder */
+};
+
+#else
+#define KERNEL_LOAD_ADDR 0x00010000
+#define KERNEL_BOARDID_INDEX 4
+#define KERNEL_ARGS_INDEX 5
+#define KERNEL_ENTRY_INDEX 6
/* The worlds second smallest bootloader. Set r0-r2, then jump to kernel. */
static uint32_t bootloader[] = {
@@ -30,6 +56,7 @@ static uint32_t bootloader[] = {
0, /* Address of kernel args. Set by integratorcp_init. */
0 /* Kernel entry point. Set by integratorcp_init. */
};
+#endif
/* Handling for secondary CPU boot in a multicore system.
* Unlike the uniprocessor/primary CPU boot, this is platform
@@ -239,7 +266,6 @@ static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo)
fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename);
return -1;
}
-
fdt = load_device_tree(filename, &size);
if (!fdt) {
fprintf(stderr, "Couldn't open dtb file %s\n", filename);
@@ -322,8 +348,15 @@ static void do_cpu_reset(void *opaque)
env->regs[15] = info->entry & 0xfffffffe;
env->thumb = info->entry & 1;
} else {
+#ifdef TARGET_AARCH64
+ env->pstate = PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | PSR_MODE_EL1h;
+#endif
if (env == first_cpu) {
+#ifdef TARGET_AARCH64
+ env->pc = info->loader_start;
+#else
env->regs[15] = info->loader_start;
+#endif
if (!info->dtb_filename) {
if (old_param) {
set_kernel_args_old(info);
@@ -428,7 +461,7 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
}
info->initrd_size = initrd_size;
- bootloader[4] = info->board_id;
+ bootloader[KERNEL_BOARDID_INDEX] = info->board_id;
/* for device tree boot, we pass the DTB directly in r2. Otherwise
* we point to the kernel args.
@@ -443,9 +476,9 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
if (load_dtb(dtb_start, info)) {
exit(1);
}
- bootloader[5] = dtb_start;
+ bootloader[KERNEL_ARGS_INDEX] = dtb_start;
} else {
- bootloader[5] = info->loader_start + KERNEL_ARGS_ADDR;
+ bootloader[KERNEL_ARGS_INDEX] = info->loader_start + KERNEL_ARGS_ADDR;
if (info->ram_size >= (1ULL << 32)) {
fprintf(stderr, "qemu: RAM size must be less than 4GB to boot"
" Linux kernel using ATAGS (try passing a device tree"
@@ -453,7 +486,7 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
exit(1);
}
}
- bootloader[6] = entry;
+ bootloader[KERNEL_ENTRY_INDEX] = entry;
for (n = 0; n < sizeof(bootloader) / 4; n++) {
bootloader[n] = tswap32(bootloader[n]);
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 6/6] Added SMP for Aarch64 Processors.
2013-06-28 12:11 [Qemu-devel] [PATCH 1/6] Added aarch64 configure support and default configuration Mian M. Hamayun
` (3 preceding siblings ...)
2013-06-28 12:11 ` [Qemu-devel] [PATCH 5/6] Added Boot Support for Aarch64 Processor Mian M. Hamayun
@ 2013-06-28 12:11 ` Mian M. Hamayun
2013-06-29 19:24 ` Peter Maydell
2013-06-29 19:20 ` [Qemu-devel] [PATCH 1/6] Added aarch64 configure support and default configuration Peter Maydell
5 siblings, 1 reply; 20+ messages in thread
From: Mian M. Hamayun @ 2013-06-28 12:11 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexander Spyridakis, tech, kvmarm
From: Alexander Spyridakis <a.spyridakis@virtualopensystems.com>
AArch64 uses a cpu-release-addr memory location (defined in the dts) as
a way to inform secondary CPUs where to jump to and enter their holding
pen. Inject a very simple bootloader that polls this memory location,
until the primary CPU sets it to the right address.
Signed-off-by: Alexander Spyridakis <a.spyridakis@virtualopensystems.com>
---
hw/arm/boot.c | 20 +++++++++++++++++---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 94e628b..f7a97d1 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -17,6 +17,8 @@
#include "sysemu/device_tree.h"
#include "qemu/config-file.h"
+#define DSB_INSN 0xf57ff04f
+#define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */
#define KERNEL_ARGS_ADDR 0x100
#ifdef TARGET_AARCH64
@@ -40,6 +42,16 @@ static uint32_t bootloader[] = {
0x00000000 /* .word @Board ID Higher 32-bits -- Placeholder */
};
+static uint32_t smpboot[] = {
+ 0x18000085, /* ldr w5, =0x8000fff8 - mbox value for secondary CPUs */
+ 0xf94000a4, /* 1: ldr x4, [x5] - Read address to jump to */
+ 0xb4ffffe4, /* cbz x4, 1b - Check if mbox value is zero, if yes retry */
+ 0xd61f0080, /* br x4 - Branch to given address */
+ 0x8000fff8, /* mbox value */
+ 0,
+ 0
+};
+
#else
#define KERNEL_LOAD_ADDR 0x00010000
#define KERNEL_BOARDID_INDEX 4
@@ -56,7 +68,6 @@ static uint32_t bootloader[] = {
0, /* Address of kernel args. Set by integratorcp_init. */
0 /* Kernel entry point. Set by integratorcp_init. */
};
-#endif
/* Handling for secondary CPU boot in a multicore system.
* Unlike the uniprocessor/primary CPU boot, this is platform
@@ -72,8 +83,6 @@ static uint32_t bootloader[] = {
* for an interprocessor interrupt and polling a configurable
* location for the kernel secondary CPU entry point.
*/
-#define DSB_INSN 0xf57ff04f
-#define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */
static uint32_t smpboot[] = {
0xe59f2028, /* ldr r2, gic_cpu_if */
@@ -91,6 +100,7 @@ static uint32_t smpboot[] = {
0, /* gic_cpu_if: base address of GIC CPU interface */
0 /* bootreg: Boot register address is held here */
};
+#endif
static void default_write_secondary(ARMCPU *cpu,
const struct arm_boot_info *info)
@@ -115,8 +125,12 @@ static void default_reset_secondary(ARMCPU *cpu,
{
CPUARMState *env = &cpu->env;
+#ifdef TARGET_AARCH64
+ env->pc = info->smp_loader_start;
+#else
stl_phys_notdirty(info->smp_bootreg_addr, 0);
env->regs[15] = info->smp_loader_start;
+#endif
}
#define WRITE_WORD(p, value) do { \
--
1.7.9.5
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [Qemu-devel] [PATCH 6/6] Added SMP for Aarch64 Processors.
2013-06-28 12:11 ` [Qemu-devel] [PATCH 6/6] Added SMP for Aarch64 Processors Mian M. Hamayun
@ 2013-06-29 19:24 ` Peter Maydell
2013-07-01 18:18 ` Alexander Spyridakis
0 siblings, 1 reply; 20+ messages in thread
From: Peter Maydell @ 2013-06-29 19:24 UTC (permalink / raw)
To: Mian M. Hamayun; +Cc: tech, qemu-devel, kvmarm
On 28 June 2013 13:11, Mian M. Hamayun <m.hamayun@virtualopensystems.com> wrote:
> From: Alexander Spyridakis <a.spyridakis@virtualopensystems.com>
>
> AArch64 uses a cpu-release-addr memory location (defined in the dts) as
> a way to inform secondary CPUs where to jump to and enter their holding
> pen. Inject a very simple bootloader that polls this memory location,
> until the primary CPU sets it to the right address.
This and the previous patch are a bit heavy on the #ifdef TARGET_AARCH64.
I suspect the code could be restructured better to avoid that.
thanks
-- PMM
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [PATCH 6/6] Added SMP for Aarch64 Processors.
2013-06-29 19:24 ` Peter Maydell
@ 2013-07-01 18:18 ` Alexander Spyridakis
0 siblings, 0 replies; 20+ messages in thread
From: Alexander Spyridakis @ 2013-07-01 18:18 UTC (permalink / raw)
To: Peter Maydell; +Cc: tech, qemu-devel, Mian M. Hamayun, kvmarm
On 29 June 2013 21:24, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 28 June 2013 13:11, Mian M. Hamayun <m.hamayun@virtualopensystems.com> wrote:
>> From: Alexander Spyridakis <a.spyridakis@virtualopensystems.com>
>>
>> AArch64 uses a cpu-release-addr memory location (defined in the dts) as
>> a way to inform secondary CPUs where to jump to and enter their holding
>> pen. Inject a very simple bootloader that polls this memory location,
>> until the primary CPU sets it to the right address.
>
> This and the previous patch are a bit heavy on the #ifdef TARGET_AARCH64.
> I suspect the code could be restructured better to avoid that.
Fair point. Initially it was even heavier on the #ifdef usage, and for
the first version we opted for something in-between in order to get
comments first. Next version will improve this with some further
restructuring.
Regards.
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [PATCH 1/6] Added aarch64 configure support and default configuration
2013-06-28 12:11 [Qemu-devel] [PATCH 1/6] Added aarch64 configure support and default configuration Mian M. Hamayun
` (4 preceding siblings ...)
2013-06-28 12:11 ` [Qemu-devel] [PATCH 6/6] Added SMP for Aarch64 Processors Mian M. Hamayun
@ 2013-06-29 19:20 ` Peter Maydell
2013-07-01 18:46 ` Alexander Spyridakis
5 siblings, 1 reply; 20+ messages in thread
From: Peter Maydell @ 2013-06-29 19:20 UTC (permalink / raw)
To: Mian M. Hamayun; +Cc: tech, qemu-devel, kvmarm
On 28 June 2013 13:11, Mian M. Hamayun <m.hamayun@virtualopensystems.com> wrote:
> From: "Mian M. Hamayun" <m.hamayun@virtualopensystems.com>
>
> Signed-off-by: Mian M. Hamayun <m.hamayun@virtualopensystems.com>
> ---
> configure | 3 +-
> default-configs/aarch64-softmmu.mak | 83 +++++++++++++++++++++++++++++++++++
> 2 files changed, 85 insertions(+), 1 deletion(-)
> create mode 100644 default-configs/aarch64-softmmu.mak
>
> diff --git a/configure b/configure
> index b247e5b..ddec40d 100755
> --- a/configure
> +++ b/configure
> @@ -4293,10 +4293,11 @@ case "$target_name" in
> *)
> esac
> case "$target_name" in
> - arm|i386|x86_64|ppcemb|ppc|ppc64|s390x)
> + arm|aarch64|i386|x86_64|ppcemb|ppc|ppc64|s390x)
> # Make sure the target and host cpus are compatible
> if test "$kvm" = "yes" -a "$target_softmmu" = "yes" -a \
> \( "$target_name" = "$cpu" -o \
> + \( "$target_name" = "arm" -a "$cpu" = "aarch64" \) -o \
> \( "$target_name" = "ppcemb" -a "$cpu" = "ppc" \) -o \
> \( "$target_name" = "ppc64" -a "$cpu" = "ppc" \) -o \
> \( "$target_name" = "ppc" -a "$cpu" = "ppc64" \) -o \
So this is enabling support for emulating 32 bit VMs with a
QEMU running as a 64 bit process, but the commit message
doesn't mention this. Did you test that combination?
thanks
-- PMM
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [Qemu-devel] [PATCH 1/6] Added aarch64 configure support and default configuration
2013-06-29 19:20 ` [Qemu-devel] [PATCH 1/6] Added aarch64 configure support and default configuration Peter Maydell
@ 2013-07-01 18:46 ` Alexander Spyridakis
2013-07-01 19:22 ` Peter Maydell
0 siblings, 1 reply; 20+ messages in thread
From: Alexander Spyridakis @ 2013-07-01 18:46 UTC (permalink / raw)
To: Peter Maydell; +Cc: tech, qemu-devel, Mian M. Hamayun, kvmarm
On 29 June 2013 21:20, Peter Maydell <peter.maydell@linaro.org> wrote:
> So this is enabling support for emulating 32 bit VMs with a
> QEMU running as a 64 bit process, but the commit message
> doesn't mention this. Did you test that combination?
Nope, this case is not handled. Currently it won't crash but of course
won't boot either. Definitely worth looking into, at the very minimum
it should gracefully deny execution.
Regards.
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [PATCH 1/6] Added aarch64 configure support and default configuration
2013-07-01 18:46 ` Alexander Spyridakis
@ 2013-07-01 19:22 ` Peter Maydell
2013-07-01 19:24 ` Peter Maydell
0 siblings, 1 reply; 20+ messages in thread
From: Peter Maydell @ 2013-07-01 19:22 UTC (permalink / raw)
To: Alexander Spyridakis; +Cc: tech, qemu-devel, Mian M. Hamayun, kvmarm
On 1 July 2013 19:46, Alexander Spyridakis
<a.spyridakis@virtualopensystems.com> wrote:
> On 29 June 2013 21:20, Peter Maydell <peter.maydell@linaro.org> wrote:
>> So this is enabling support for emulating 32 bit VMs with a
>> QEMU running as a 64 bit process, but the commit message
>> doesn't mention this. Did you test that combination?
Actually I wasn't quite right here -- in fact
\( "$target_name" = "arm" -a "$cpu" = "aarch64" \)
is the case where you're building a QEMU running as a 64 bit binary
but only supporting 32 bit CPUs. In particular this would try to build
a 64 bit binary but with QEMU's copy of the 32 bit kernel headers:
I'm not sure that's expected (by the kernel folk) to work at all. If not,
we should just not put the line into configure in the first place.
Note that that still leaves the case of "built aarch64-softmmu
with KVM support and user used -cpu cortex-a15" which you can only
catch at runtime. My guess is that will either (a) work or (b) be
caught already by the KVM_ARM_VCPU_INIT ioctl failing because we asked
for KVM_ARM_TARGET_CORTEX_A15 and the kernel didn't support it.
Either way, it seems like a more sensible way to support the 32-on-64
case when we eventually choose to do so.
> Nope, this case is not handled. Currently it won't crash but of course
> won't boot either. Definitely worth looking into, at the very minimum
> it should gracefully deny execution.
Yes, in general I'm happy for us not to support 32-bit-VM-on-64-host
initially, as long as it fails gracefully.
thanks
-- PMM
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [Qemu-devel] [PATCH 1/6] Added aarch64 configure support and default configuration
2013-07-01 19:22 ` Peter Maydell
@ 2013-07-01 19:24 ` Peter Maydell
0 siblings, 0 replies; 20+ messages in thread
From: Peter Maydell @ 2013-07-01 19:24 UTC (permalink / raw)
To: Alexander Spyridakis; +Cc: tech, qemu-devel, Mian M. Hamayun, kvmarm
On 1 July 2013 20:22, Peter Maydell <peter.maydell@linaro.org> wrote:
In particular this would try to build
> a 64 bit binary but with QEMU's copy of the 32 bit kernel headers:
> I'm not sure that's expected (by the kernel folk) to work at all. If not,
> we should just not put the line into configure in the first place.
Sorry, this bit is wrong; ignore it. We pick the kernel headers based
on $cpu, not $target, so get the aarch64 ones whether we're building
arm-softmmu or aarch64-softmmu.
-- PMM
^ permalink raw reply [flat|nested] 20+ messages in thread