From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36018) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UtOkM-0001K5-V7 for qemu-devel@nongnu.org; Sun, 30 Jun 2013 17:01:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UtOkK-0003kY-IE for qemu-devel@nongnu.org; Sun, 30 Jun 2013 17:01:22 -0400 Received: from cantor2.suse.de ([195.135.220.15]:58286 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UtOkK-0003kB-2g for qemu-devel@nongnu.org; Sun, 30 Jun 2013 17:01:20 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 30 Jun 2013 23:00:58 +0200 Message-Id: <1372626065-6043-9-git-send-email-afaerber@suse.de> In-Reply-To: <1372626065-6043-1-git-send-email-afaerber@suse.de> References: <1372626065-6043-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH RFC 08/15] cpu/a9mpcore: Embed ARMMPTimerState List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook From: Andreas F=C3=A4rber Prepares for QOM realize. Signed-off-by: Andreas F=C3=A4rber --- hw/cpu/a9mpcore.c | 46 +++++++++++++++++++++-------------- hw/timer/arm_mptimer.c | 35 ++++----------------------- include/hw/timer/arm_mptimer.h | 54 ++++++++++++++++++++++++++++++++++++= ++++++ 3 files changed, 86 insertions(+), 49 deletions(-) create mode 100644 include/hw/timer/arm_mptimer.h diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index b7148fa..48f5897 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -11,6 +11,7 @@ #include "hw/sysbus.h" #include "hw/intc/gic_internal.h" #include "hw/misc/a9scu.h" +#include "hw/timer/arm_mptimer.h" =20 #define TYPE_A9MPCORE_PRIV "a9mpcore_priv" #define A9MPCORE_PRIV(obj) \ @@ -23,12 +24,12 @@ typedef struct A9MPPrivState { =20 uint32_t num_cpu; MemoryRegion container; - DeviceState *mptimer; - DeviceState *wdt; uint32_t num_irq; =20 GICState gic; A9SCUState scu; + ARMMPTimerState mptimer; + ARMMPTimerState wdt; } A9MPPrivState; =20 static void a9mp_priv_set_irq(void *opaque, int irq, int level) @@ -54,12 +55,28 @@ static void a9mp_priv_initfn(Object *obj) sbd =3D SYS_BUS_DEVICE(&s->scu); memory_region_add_subregion(&s->container, 0, sysbus_mmio_get_region(sbd, 0)); + + object_initialize(&s->mptimer, TYPE_ARM_MP_TIMER); + qdev_set_parent_bus(DEVICE(&s->mptimer), sysbus_get_default()); + + object_initialize(&s->wdt, TYPE_ARM_MP_TIMER); + qdev_set_parent_bus(DEVICE(&s->wdt), sysbus_get_default()); + + /* Note that the A9 exposes only the "timer/watchdog for this core" + * memory region, not the "timer/watchdog for core X" ones 11MPcore = has. + */ + sbd =3D SYS_BUS_DEVICE(&s->mptimer); + memory_region_add_subregion(&s->container, 0x600, + sysbus_mmio_get_region(sbd, 0)); + sbd =3D SYS_BUS_DEVICE(&s->wdt); + memory_region_add_subregion(&s->container, 0x620, + sysbus_mmio_get_region(sbd, 0)); } =20 static int a9mp_priv_init(SysBusDevice *dev) { A9MPPrivState *s =3D A9MPCORE_PRIV(dev); - DeviceState *gicdev, *scudev; + DeviceState *gicdev, *scudev, *mptimerdev, *wdtdev; SysBusDevice *timerbusdev, *wdtbusdev, *gicbusdev; int i; =20 @@ -79,15 +96,15 @@ static int a9mp_priv_init(SysBusDevice *dev) qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); qdev_init_nofail(scudev); =20 - s->mptimer =3D qdev_create(NULL, "arm_mptimer"); - qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu); - qdev_init_nofail(s->mptimer); - timerbusdev =3D SYS_BUS_DEVICE(s->mptimer); + mptimerdev =3D DEVICE(&s->mptimer); + qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu); + qdev_init_nofail(mptimerdev); + timerbusdev =3D SYS_BUS_DEVICE(&s->mptimer); =20 - s->wdt =3D qdev_create(NULL, "arm_mptimer"); - qdev_prop_set_uint32(s->wdt, "num-cpu", s->num_cpu); - qdev_init_nofail(s->wdt); - wdtbusdev =3D SYS_BUS_DEVICE(s->wdt); + wdtdev =3D DEVICE(&s->wdt); + qdev_prop_set_uint32(wdtdev, "num-cpu", s->num_cpu); + qdev_init_nofail(wdtdev); + wdtbusdev =3D SYS_BUS_DEVICE(&s->wdt); =20 /* Memory map (addresses are offsets from PERIPHBASE): * 0x0000-0x00ff -- Snoop Control Unit @@ -103,13 +120,6 @@ static int a9mp_priv_init(SysBusDevice *dev) /* GIC CPU interface */ memory_region_add_subregion(&s->container, 0x100, sysbus_mmio_get_region(gicbusdev, 1)); - /* Note that the A9 exposes only the "timer/watchdog for this core" - * memory region, not the "timer/watchdog for core X" ones 11MPcore = has. - */ - memory_region_add_subregion(&s->container, 0x600, - sysbus_mmio_get_region(timerbusdev, 0)); - memory_region_add_subregion(&s->container, 0x620, - sysbus_mmio_get_region(wdtbusdev, 0)); memory_region_add_subregion(&s->container, 0x1000, sysbus_mmio_get_region(gicbusdev, 0)); =20 diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c index a19ffa3..5558f40 100644 --- a/hw/timer/arm_mptimer.c +++ b/hw/timer/arm_mptimer.c @@ -19,41 +19,13 @@ * with this program; if not, see . */ =20 -#include "hw/sysbus.h" +#include "hw/timer/arm_mptimer.h" #include "qemu/timer.h" =20 /* This device implements the per-cpu private timer and watchdog block * which is used in both the ARM11MPCore and Cortex-A9MP. */ =20 -#define MAX_CPUS 4 - -/* State of a single timer or watchdog block */ -typedef struct { - uint32_t count; - uint32_t load; - uint32_t control; - uint32_t status; - int64_t tick; - QEMUTimer *timer; - qemu_irq irq; - MemoryRegion iomem; -} TimerBlock; - -#define TYPE_ARM_MP_TIMER "arm_mptimer" -#define ARM_MP_TIMER(obj) \ - OBJECT_CHECK(ARMMPTimerState, (obj), TYPE_ARM_MP_TIMER) - -typedef struct { - /*< private >*/ - SysBusDevice parent_obj; - /*< public >*/ - - uint32_t num_cpu; - TimerBlock timerblock[MAX_CPUS]; - MemoryRegion iomem; -} ARMMPTimerState; - static inline int get_current_cpu(ARMMPTimerState *s) { CPUState *cpu_single_cpu =3D ENV_GET_CPU(cpu_single_env); @@ -241,8 +213,9 @@ static void arm_mptimer_realize(DeviceState *dev, Err= or **errp) ARMMPTimerState *s =3D ARM_MP_TIMER(dev); int i; =20 - if (s->num_cpu < 1 || s->num_cpu > MAX_CPUS) { - hw_error("%s: num-cpu must be between 1 and %d\n", __func__, MAX= _CPUS); + if (s->num_cpu < 1 || s->num_cpu > ARM_MPTIMER_MAX_CPUS) { + hw_error("%s: num-cpu must be between 1 and %d\n", + __func__, ARM_MPTIMER_MAX_CPUS); } /* We implement one timer block per CPU, and expose multiple MMIO re= gions: * * region 0 is "timer for this core" diff --git a/include/hw/timer/arm_mptimer.h b/include/hw/timer/arm_mptime= r.h new file mode 100644 index 0000000..40a5fee --- /dev/null +++ b/include/hw/timer/arm_mptimer.h @@ -0,0 +1,54 @@ +/* + * Private peripheral timer/watchdog blocks for ARM 11MPCore and A9MP + * + * Copyright (c) 2006-2007 CodeSourcery. + * Copyright (c) 2011 Linaro Limited + * Written by Paul Brook, Peter Maydell + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License alo= ng + * with this program; if not, see . + */ +#ifndef HW_TIMER_ARM_MPTIMER_H +#define HW_TIMER_ARM_MPTIMER_H + +#include "hw/sysbus.h" + +#define ARM_MPTIMER_MAX_CPUS 4 + +/* State of a single timer or watchdog block */ +typedef struct { + uint32_t count; + uint32_t load; + uint32_t control; + uint32_t status; + int64_t tick; + QEMUTimer *timer; + qemu_irq irq; + MemoryRegion iomem; +} TimerBlock; + +#define TYPE_ARM_MP_TIMER "arm_mptimer" +#define ARM_MP_TIMER(obj) \ + OBJECT_CHECK(ARMMPTimerState, (obj), TYPE_ARM_MP_TIMER) + +typedef struct { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + uint32_t num_cpu; + TimerBlock timerblock[ARM_MPTIMER_MAX_CPUS]; + MemoryRegion iomem; +} ARMMPTimerState; + +#endif --=20 1.8.1.4