* [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset
@ 2013-07-01 17:34 Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 01/21] target-arm: Abstract out load/store from a vaddr in AArch32 Peter Maydell
` (22 more replies)
0 siblings, 23 replies; 29+ messages in thread
From: Peter Maydell @ 2013-07-01 17:34 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Schwab, Alexander Graf, Mian M. Hamayun, patches
This patchset is v5 of the "preparation patchset" that started
off with Alex, was passed to John Rigby and now to me.
Things I've done to it:
* various bits of cleanup for style and other minor things
* a little shuffling and splitting of patches
* made the 32 bit CPUs work in aarch64-softmmu
* given aarch64 its own cpu_loop() in linux-user/main.c
* made sure NWFPE doesn't sneak into aarch64-linux-user
* let aarch64 have a nearly clean slate for tb_flags
Individual patches have a summary of my changes in the commit.
I've left the 'global cpu_env variable' patch alone since
there wasn't any consensus about what the best approach was;
it's a pretty minor (and textually localized) thing anyway so
easy to fix in future if it becomes an actual problem.
With these patches:
* new target aarch64-linux-user, which will run but
SIGILL on all instructions
* new target aarch64-softmmu, which will run all the 32 bit
CPUs and board models; however there is no 64 bit CPU
defined so it's a bit pointless except as a demonstration
that we haven't broken the 32 bit code.
I'm generally happy with the patchset and think it could
be committed (except for the last two default-configs patchs
which actually enable the new targets), apart from the fact
that it's not actually terribly useful yet.
There's one patch in here which is obviously going to clash
with my "move cpu_set_tls and cpu_clone_regs to linux-user"
patch, but it will be easy enough to fix when that goes in.
Note that in general the 'signed-off-by:' lines from people
other than me should be taken to indicate credit/authorship
rather than "I'm happy with this patchset", given that I've
changed the patches as they passed through my hands.
Alexander Graf (14):
target-arm: Extract the disas struct to a header file
target-arm: Export cpu_env
target-arm: Fix target_ulong/uint32_t confusions
target-arm: Prepare translation for AArch64 code
target-arm: Add AArch64 translation stub
gdbstub: Add AArch64 support
linux-user: Don't treat AArch64 cpu names specially
linux-user: Add syscall number definitions for AArch64
linux-user: Fix up AArch64 syscall handlers
target-arm: Implement cpu_set_tls() and cpu_clone_regs() for AArch64
linux-user: Add AArch64 termbits.h definitions
linux-user: Add AArch64 support
linux-user: AArch64 requires at least 3.8.0
configure: Add handling code for AArch64 targets
Andreas Schwab (1):
linux-user: Add signal handling for AArch64
Peter Maydell (6):
target-arm: Abstract out load/store from a vaddr in AArch32
target-arm: Pass DisasContext* to gen_set_pc_im()
linux-user: Add cpu loop for AArch64
linux-user: Make sure NWFPE code is 32 bit ARM only
default-configs: Add config for aarch64-linux-user
default-configs: Add config for aarch64-softmmu
configure | 9 +-
default-configs/aarch64-linux-user.mak | 3 +
default-configs/aarch64-softmmu.mak | 82 ++++++
gdb-xml/aarch64-core.xml | 46 ++++
gdb-xml/aarch64-fpu.xml | 86 +++++++
gdbstub.c | 53 ++++
linux-user/aarch64/syscall.h | 8 +
linux-user/aarch64/syscall_nr.h | 323 ++++++++++++++++++++++++
linux-user/aarch64/target_signal.h | 29 +++
linux-user/aarch64/termbits.h | 220 +++++++++++++++++
linux-user/cpu-uname.c | 3 +-
linux-user/elfload.c | 15 +-
linux-user/main.c | 98 ++++++++
linux-user/qemu.h | 4 +-
linux-user/signal.c | 254 +++++++++++++++++++
linux-user/syscall.c | 10 +-
linux-user/syscall_defs.h | 28 ++-
target-arm/Makefile.objs | 1 +
target-arm/cpu.c | 8 +
target-arm/cpu.h | 152 +++++++++---
target-arm/machine.c | 8 +-
target-arm/translate-a64.c | 137 ++++++++++
target-arm/translate.c | 426 ++++++++++++++++++++------------
target-arm/translate.h | 55 +++++
24 files changed, 1853 insertions(+), 205 deletions(-)
create mode 100644 default-configs/aarch64-linux-user.mak
create mode 100644 default-configs/aarch64-softmmu.mak
create mode 100644 gdb-xml/aarch64-core.xml
create mode 100644 gdb-xml/aarch64-fpu.xml
create mode 100644 linux-user/aarch64/syscall.h
create mode 100644 linux-user/aarch64/syscall_nr.h
create mode 100644 linux-user/aarch64/target_signal.h
create mode 100644 linux-user/aarch64/termbits.h
create mode 100644 target-arm/translate-a64.c
create mode 100644 target-arm/translate.h
--
1.7.9.5
^ permalink raw reply [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH v5 01/21] target-arm: Abstract out load/store from a vaddr in AArch32
2013-07-01 17:34 [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset Peter Maydell
@ 2013-07-01 17:35 ` Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 02/21] target-arm: Extract the disas struct to a header file Peter Maydell
` (21 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Peter Maydell @ 2013-07-01 17:35 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Schwab, Alexander Graf, Mian M. Hamayun, patches
AArch32 code (ie traditional 32 bit world) expects to be
able to pass a vaddr in a TCGv_i32. However when QEMU is
compiled with TARGET_LONG_BITS=32 the TCG load/store
functions take a TCGv_i64. Abstract out load/store with
a 32 bit vaddr so we have a place to put the zero extension
of the vaddr and the extension/truncation of the data value.
Apart from the function definitions most of this patch is
a simple s/tcg_gen_qemu_/gen_aa32_/.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/translate.c | 310 +++++++++++++++++++++++++++++++-----------------
1 file changed, 198 insertions(+), 112 deletions(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index af2aef2..1618524 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -841,6 +841,90 @@ static inline void store_reg_from_load(CPUARMState *env, DisasContext *s,
}
}
+/* Abstractions of "generate code to do a guest load/store for
+ * AArch32", where a vaddr is always 32 bits (and is zero
+ * extended if we're a 64 bit core) and data is also
+ * 32 bits unless specifically doing a 64 bit access.
+ * These functions work like tcg_gen_qemu_{ld,st}* except
+ * that their arguments are TCGv_i32 rather than TCGv.
+ */
+#if TARGET_LONG_BITS == 32
+
+#define DO_GEN_LD(OP) \
+static inline void gen_aa32_##OP(TCGv_i32 val, TCGv_i32 addr, int index) \
+{ \
+ tcg_gen_qemu_##OP(val, addr, index); \
+}
+
+#define DO_GEN_ST(OP) \
+static inline void gen_aa32_##OP(TCGv_i32 val, TCGv_i32 addr, int index) \
+{ \
+ tcg_gen_qemu_##OP(val, addr, index); \
+}
+
+static inline void gen_aa32_ld64(TCGv_i64 val, TCGv_i32 addr, int index)
+{
+ tcg_gen_qemu_ld64(val, addr, index);
+}
+
+static inline void gen_aa32_st64(TCGv_i64 val, TCGv_i32 addr, int index)
+{
+ tcg_gen_qemu_st64(val, addr, index);
+}
+
+#else
+
+#define DO_GEN_LD(OP) \
+static inline void gen_aa32_##OP(TCGv_i32 val, TCGv_i32 addr, int index) \
+{ \
+ TCGv addr64 = tcg_temp_new(); \
+ TCGv val64 = tcg_temp_new(); \
+ tcg_gen_extu_i32_i64(addr64, addr); \
+ tcg_gen_qemu_##OP(val64, addr64, index); \
+ tcg_temp_free(addr64); \
+ tcg_gen_trunc_i64_i32(val, val64); \
+ tcg_temp_free(val64); \
+}
+
+#define DO_GEN_ST(OP) \
+static inline void gen_aa32_##OP(TCGv_i32 val, TCGv_i32 addr, int index) \
+{ \
+ TCGv addr64 = tcg_temp_new(); \
+ TCGv val64 = tcg_temp_new(); \
+ tcg_gen_extu_i32_i64(addr64, addr); \
+ tcg_gen_extu_i32_i64(val64, val); \
+ tcg_gen_qemu_##OP(val64, addr64, index); \
+ tcg_temp_free(addr64); \
+ tcg_temp_free(val64); \
+}
+
+static inline void gen_aa32_ld64(TCGv_i64 val, TCGv_i32 addr, int index)
+{
+ TCGv addr64 = tcg_temp_new();
+ tcg_gen_extu_i32_i64(addr64, addr);
+ tcg_gen_qemu_ld64(val, addr64, index);
+ tcg_temp_free(addr64);
+}
+
+static inline void gen_aa32_st64(TCGv_i64 val, TCGv_i32 addr, int index)
+{
+ TCGv addr64 = tcg_temp_new();
+ tcg_gen_extu_i32_i64(addr64, addr);
+ tcg_gen_qemu_st64(val, addr64, index);
+ tcg_temp_free(addr64);
+}
+
+#endif
+
+DO_GEN_LD(ld8s)
+DO_GEN_LD(ld8u)
+DO_GEN_LD(ld16s)
+DO_GEN_LD(ld16u)
+DO_GEN_LD(ld32u)
+DO_GEN_ST(st8)
+DO_GEN_ST(st16)
+DO_GEN_ST(st32)
+
static inline void gen_set_pc_im(uint32_t val)
{
tcg_gen_movi_i32(cpu_R[15], val);
@@ -1070,18 +1154,20 @@ VFP_GEN_FIX(ulto)
static inline void gen_vfp_ld(DisasContext *s, int dp, TCGv_i32 addr)
{
- if (dp)
- tcg_gen_qemu_ld64(cpu_F0d, addr, IS_USER(s));
- else
- tcg_gen_qemu_ld32u(cpu_F0s, addr, IS_USER(s));
+ if (dp) {
+ gen_aa32_ld64(cpu_F0d, addr, IS_USER(s));
+ } else {
+ gen_aa32_ld32u(cpu_F0s, addr, IS_USER(s));
+ }
}
static inline void gen_vfp_st(DisasContext *s, int dp, TCGv_i32 addr)
{
- if (dp)
- tcg_gen_qemu_st64(cpu_F0d, addr, IS_USER(s));
- else
- tcg_gen_qemu_st32(cpu_F0s, addr, IS_USER(s));
+ if (dp) {
+ gen_aa32_st64(cpu_F0d, addr, IS_USER(s));
+ } else {
+ gen_aa32_st32(cpu_F0s, addr, IS_USER(s));
+ }
}
static inline long
@@ -1418,24 +1504,24 @@ static int disas_iwmmxt_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
if (insn & ARM_CP_RW_BIT) {
if ((insn >> 28) == 0xf) { /* WLDRW wCx */
tmp = tcg_temp_new_i32();
- tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, IS_USER(s));
iwmmxt_store_creg(wrd, tmp);
} else {
i = 1;
if (insn & (1 << 8)) {
if (insn & (1 << 22)) { /* WLDRD */
- tcg_gen_qemu_ld64(cpu_M0, addr, IS_USER(s));
+ gen_aa32_ld64(cpu_M0, addr, IS_USER(s));
i = 0;
} else { /* WLDRW wRd */
tmp = tcg_temp_new_i32();
- tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, IS_USER(s));
}
} else {
tmp = tcg_temp_new_i32();
if (insn & (1 << 22)) { /* WLDRH */
- tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
+ gen_aa32_ld16u(tmp, addr, IS_USER(s));
} else { /* WLDRB */
- tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
+ gen_aa32_ld8u(tmp, addr, IS_USER(s));
}
}
if (i) {
@@ -1447,24 +1533,24 @@ static int disas_iwmmxt_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
} else {
if ((insn >> 28) == 0xf) { /* WSTRW wCx */
tmp = iwmmxt_load_creg(wrd);
- tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, IS_USER(s));
} else {
gen_op_iwmmxt_movq_M0_wRn(wrd);
tmp = tcg_temp_new_i32();
if (insn & (1 << 8)) {
if (insn & (1 << 22)) { /* WSTRD */
- tcg_gen_qemu_st64(cpu_M0, addr, IS_USER(s));
+ gen_aa32_st64(cpu_M0, addr, IS_USER(s));
} else { /* WSTRW wRd */
tcg_gen_trunc_i64_i32(tmp, cpu_M0);
- tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, IS_USER(s));
}
} else {
if (insn & (1 << 22)) { /* WSTRH */
tcg_gen_trunc_i64_i32(tmp, cpu_M0);
- tcg_gen_qemu_st16(tmp, addr, IS_USER(s));
+ gen_aa32_st16(tmp, addr, IS_USER(s));
} else { /* WSTRB */
tcg_gen_trunc_i64_i32(tmp, cpu_M0);
- tcg_gen_qemu_st8(tmp, addr, IS_USER(s));
+ gen_aa32_st8(tmp, addr, IS_USER(s));
}
}
}
@@ -2529,15 +2615,15 @@ static TCGv_i32 gen_load_and_replicate(DisasContext *s, TCGv_i32 addr, int size)
TCGv_i32 tmp = tcg_temp_new_i32();
switch (size) {
case 0:
- tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
+ gen_aa32_ld8u(tmp, addr, IS_USER(s));
gen_neon_dup_u8(tmp, 0);
break;
case 1:
- tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
+ gen_aa32_ld16u(tmp, addr, IS_USER(s));
gen_neon_dup_low16(tmp);
break;
case 2:
- tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, IS_USER(s));
break;
default: /* Avoid compiler warnings. */
abort();
@@ -3814,11 +3900,11 @@ static int disas_neon_ls_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
if (size == 3) {
tmp64 = tcg_temp_new_i64();
if (load) {
- tcg_gen_qemu_ld64(tmp64, addr, IS_USER(s));
+ gen_aa32_ld64(tmp64, addr, IS_USER(s));
neon_store_reg64(tmp64, rd);
} else {
neon_load_reg64(tmp64, rd);
- tcg_gen_qemu_st64(tmp64, addr, IS_USER(s));
+ gen_aa32_st64(tmp64, addr, IS_USER(s));
}
tcg_temp_free_i64(tmp64);
tcg_gen_addi_i32(addr, addr, stride);
@@ -3827,21 +3913,21 @@ static int disas_neon_ls_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
if (size == 2) {
if (load) {
tmp = tcg_temp_new_i32();
- tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, IS_USER(s));
neon_store_reg(rd, pass, tmp);
} else {
tmp = neon_load_reg(rd, pass);
- tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, IS_USER(s));
tcg_temp_free_i32(tmp);
}
tcg_gen_addi_i32(addr, addr, stride);
} else if (size == 1) {
if (load) {
tmp = tcg_temp_new_i32();
- tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
+ gen_aa32_ld16u(tmp, addr, IS_USER(s));
tcg_gen_addi_i32(addr, addr, stride);
tmp2 = tcg_temp_new_i32();
- tcg_gen_qemu_ld16u(tmp2, addr, IS_USER(s));
+ gen_aa32_ld16u(tmp2, addr, IS_USER(s));
tcg_gen_addi_i32(addr, addr, stride);
tcg_gen_shli_i32(tmp2, tmp2, 16);
tcg_gen_or_i32(tmp, tmp, tmp2);
@@ -3851,10 +3937,10 @@ static int disas_neon_ls_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
tmp = neon_load_reg(rd, pass);
tmp2 = tcg_temp_new_i32();
tcg_gen_shri_i32(tmp2, tmp, 16);
- tcg_gen_qemu_st16(tmp, addr, IS_USER(s));
+ gen_aa32_st16(tmp, addr, IS_USER(s));
tcg_temp_free_i32(tmp);
tcg_gen_addi_i32(addr, addr, stride);
- tcg_gen_qemu_st16(tmp2, addr, IS_USER(s));
+ gen_aa32_st16(tmp2, addr, IS_USER(s));
tcg_temp_free_i32(tmp2);
tcg_gen_addi_i32(addr, addr, stride);
}
@@ -3863,7 +3949,7 @@ static int disas_neon_ls_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
TCGV_UNUSED_I32(tmp2);
for (n = 0; n < 4; n++) {
tmp = tcg_temp_new_i32();
- tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
+ gen_aa32_ld8u(tmp, addr, IS_USER(s));
tcg_gen_addi_i32(addr, addr, stride);
if (n == 0) {
tmp2 = tmp;
@@ -3883,7 +3969,7 @@ static int disas_neon_ls_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
} else {
tcg_gen_shri_i32(tmp, tmp2, n * 8);
}
- tcg_gen_qemu_st8(tmp, addr, IS_USER(s));
+ gen_aa32_st8(tmp, addr, IS_USER(s));
tcg_temp_free_i32(tmp);
tcg_gen_addi_i32(addr, addr, stride);
}
@@ -4007,13 +4093,13 @@ static int disas_neon_ls_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
tmp = tcg_temp_new_i32();
switch (size) {
case 0:
- tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
+ gen_aa32_ld8u(tmp, addr, IS_USER(s));
break;
case 1:
- tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
+ gen_aa32_ld16u(tmp, addr, IS_USER(s));
break;
case 2:
- tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, IS_USER(s));
break;
default: /* Avoid compiler warnings. */
abort();
@@ -4031,13 +4117,13 @@ static int disas_neon_ls_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
tcg_gen_shri_i32(tmp, tmp, shift);
switch (size) {
case 0:
- tcg_gen_qemu_st8(tmp, addr, IS_USER(s));
+ gen_aa32_st8(tmp, addr, IS_USER(s));
break;
case 1:
- tcg_gen_qemu_st16(tmp, addr, IS_USER(s));
+ gen_aa32_st16(tmp, addr, IS_USER(s));
break;
case 2:
- tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, IS_USER(s));
break;
}
tcg_temp_free_i32(tmp);
@@ -6451,14 +6537,14 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
switch (size) {
case 0:
- tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
+ gen_aa32_ld8u(tmp, addr, IS_USER(s));
break;
case 1:
- tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
+ gen_aa32_ld16u(tmp, addr, IS_USER(s));
break;
case 2:
case 3:
- tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, IS_USER(s));
break;
default:
abort();
@@ -6469,7 +6555,7 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
TCGv_i32 tmp2 = tcg_temp_new_i32();
tcg_gen_addi_i32(tmp2, addr, 4);
tmp = tcg_temp_new_i32();
- tcg_gen_qemu_ld32u(tmp, tmp2, IS_USER(s));
+ gen_aa32_ld32u(tmp, tmp2, IS_USER(s));
tcg_temp_free_i32(tmp2);
tcg_gen_mov_i32(cpu_exclusive_high, tmp);
store_reg(s, rt2, tmp);
@@ -6511,14 +6597,14 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
tmp = tcg_temp_new_i32();
switch (size) {
case 0:
- tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
+ gen_aa32_ld8u(tmp, addr, IS_USER(s));
break;
case 1:
- tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
+ gen_aa32_ld16u(tmp, addr, IS_USER(s));
break;
case 2:
case 3:
- tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, IS_USER(s));
break;
default:
abort();
@@ -6529,7 +6615,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
TCGv_i32 tmp2 = tcg_temp_new_i32();
tcg_gen_addi_i32(tmp2, addr, 4);
tmp = tcg_temp_new_i32();
- tcg_gen_qemu_ld32u(tmp, tmp2, IS_USER(s));
+ gen_aa32_ld32u(tmp, tmp2, IS_USER(s));
tcg_temp_free_i32(tmp2);
tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_high, fail_label);
tcg_temp_free_i32(tmp);
@@ -6537,14 +6623,14 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
tmp = load_reg(s, rt);
switch (size) {
case 0:
- tcg_gen_qemu_st8(tmp, addr, IS_USER(s));
+ gen_aa32_st8(tmp, addr, IS_USER(s));
break;
case 1:
- tcg_gen_qemu_st16(tmp, addr, IS_USER(s));
+ gen_aa32_st16(tmp, addr, IS_USER(s));
break;
case 2:
case 3:
- tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, IS_USER(s));
break;
default:
abort();
@@ -6553,7 +6639,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
if (size == 3) {
tcg_gen_addi_i32(addr, addr, 4);
tmp = load_reg(s, rt2);
- tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, IS_USER(s));
tcg_temp_free_i32(tmp);
}
tcg_gen_movi_i32(cpu_R[rd], 0);
@@ -6600,11 +6686,11 @@ static void gen_srs(DisasContext *s,
}
tcg_gen_addi_i32(addr, addr, offset);
tmp = load_reg(s, 14);
- tcg_gen_qemu_st32(tmp, addr, 0);
+ gen_aa32_st32(tmp, addr, 0);
tcg_temp_free_i32(tmp);
tmp = load_cpu_field(spsr);
tcg_gen_addi_i32(addr, addr, 4);
- tcg_gen_qemu_st32(tmp, addr, 0);
+ gen_aa32_st32(tmp, addr, 0);
tcg_temp_free_i32(tmp);
if (writeback) {
switch (amode) {
@@ -6749,10 +6835,10 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
tcg_gen_addi_i32(addr, addr, offset);
/* Load PC into tmp and CPSR into tmp2. */
tmp = tcg_temp_new_i32();
- tcg_gen_qemu_ld32u(tmp, addr, 0);
+ gen_aa32_ld32u(tmp, addr, 0);
tcg_gen_addi_i32(addr, addr, 4);
tmp2 = tcg_temp_new_i32();
- tcg_gen_qemu_ld32u(tmp2, addr, 0);
+ gen_aa32_ld32u(tmp2, addr, 0);
if (insn & (1 << 21)) {
/* Base writeback. */
switch (i) {
@@ -7328,11 +7414,11 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
tmp = load_reg(s, rm);
tmp2 = tcg_temp_new_i32();
if (insn & (1 << 22)) {
- tcg_gen_qemu_ld8u(tmp2, addr, IS_USER(s));
- tcg_gen_qemu_st8(tmp, addr, IS_USER(s));
+ gen_aa32_ld8u(tmp2, addr, IS_USER(s));
+ gen_aa32_st8(tmp, addr, IS_USER(s));
} else {
- tcg_gen_qemu_ld32u(tmp2, addr, IS_USER(s));
- tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp2, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, IS_USER(s));
}
tcg_temp_free_i32(tmp);
tcg_temp_free_i32(addr);
@@ -7354,14 +7440,14 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
tmp = tcg_temp_new_i32();
switch(sh) {
case 1:
- tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
+ gen_aa32_ld16u(tmp, addr, IS_USER(s));
break;
case 2:
- tcg_gen_qemu_ld8s(tmp, addr, IS_USER(s));
+ gen_aa32_ld8s(tmp, addr, IS_USER(s));
break;
default:
case 3:
- tcg_gen_qemu_ld16s(tmp, addr, IS_USER(s));
+ gen_aa32_ld16s(tmp, addr, IS_USER(s));
break;
}
load = 1;
@@ -7371,21 +7457,21 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
if (sh & 1) {
/* store */
tmp = load_reg(s, rd);
- tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, IS_USER(s));
tcg_temp_free_i32(tmp);
tcg_gen_addi_i32(addr, addr, 4);
tmp = load_reg(s, rd + 1);
- tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, IS_USER(s));
tcg_temp_free_i32(tmp);
load = 0;
} else {
/* load */
tmp = tcg_temp_new_i32();
- tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, IS_USER(s));
store_reg(s, rd, tmp);
tcg_gen_addi_i32(addr, addr, 4);
tmp = tcg_temp_new_i32();
- tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, IS_USER(s));
rd++;
load = 1;
}
@@ -7393,7 +7479,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
} else {
/* store */
tmp = load_reg(s, rd);
- tcg_gen_qemu_st16(tmp, addr, IS_USER(s));
+ gen_aa32_st16(tmp, addr, IS_USER(s));
tcg_temp_free_i32(tmp);
load = 0;
}
@@ -7726,17 +7812,17 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
/* load */
tmp = tcg_temp_new_i32();
if (insn & (1 << 22)) {
- tcg_gen_qemu_ld8u(tmp, tmp2, i);
+ gen_aa32_ld8u(tmp, tmp2, i);
} else {
- tcg_gen_qemu_ld32u(tmp, tmp2, i);
+ gen_aa32_ld32u(tmp, tmp2, i);
}
} else {
/* store */
tmp = load_reg(s, rd);
if (insn & (1 << 22)) {
- tcg_gen_qemu_st8(tmp, tmp2, i);
+ gen_aa32_st8(tmp, tmp2, i);
} else {
- tcg_gen_qemu_st32(tmp, tmp2, i);
+ gen_aa32_st32(tmp, tmp2, i);
}
tcg_temp_free_i32(tmp);
}
@@ -7803,7 +7889,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
if (insn & (1 << 20)) {
/* load */
tmp = tcg_temp_new_i32();
- tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, IS_USER(s));
if (user) {
tmp2 = tcg_const_i32(i);
gen_helper_set_user_reg(cpu_env, tmp2, tmp);
@@ -7830,7 +7916,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
} else {
tmp = load_reg(s, i);
}
- tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, IS_USER(s));
tcg_temp_free_i32(tmp);
}
j++;
@@ -8089,20 +8175,20 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
if (insn & (1 << 20)) {
/* ldrd */
tmp = tcg_temp_new_i32();
- tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, IS_USER(s));
store_reg(s, rs, tmp);
tcg_gen_addi_i32(addr, addr, 4);
tmp = tcg_temp_new_i32();
- tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, IS_USER(s));
store_reg(s, rd, tmp);
} else {
/* strd */
tmp = load_reg(s, rs);
- tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, IS_USER(s));
tcg_temp_free_i32(tmp);
tcg_gen_addi_i32(addr, addr, 4);
tmp = load_reg(s, rd);
- tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, IS_USER(s));
tcg_temp_free_i32(tmp);
}
if (insn & (1 << 21)) {
@@ -8140,11 +8226,11 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
tcg_gen_add_i32(addr, addr, tmp);
tcg_temp_free_i32(tmp);
tmp = tcg_temp_new_i32();
- tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
+ gen_aa32_ld16u(tmp, addr, IS_USER(s));
} else { /* tbb */
tcg_temp_free_i32(tmp);
tmp = tcg_temp_new_i32();
- tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
+ gen_aa32_ld8u(tmp, addr, IS_USER(s));
}
tcg_temp_free_i32(addr);
tcg_gen_shli_i32(tmp, tmp, 1);
@@ -8180,10 +8266,10 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
tcg_gen_addi_i32(addr, addr, -8);
/* Load PC into tmp and CPSR into tmp2. */
tmp = tcg_temp_new_i32();
- tcg_gen_qemu_ld32u(tmp, addr, 0);
+ gen_aa32_ld32u(tmp, addr, 0);
tcg_gen_addi_i32(addr, addr, 4);
tmp2 = tcg_temp_new_i32();
- tcg_gen_qemu_ld32u(tmp2, addr, 0);
+ gen_aa32_ld32u(tmp2, addr, 0);
if (insn & (1 << 21)) {
/* Base writeback. */
if (insn & (1 << 24)) {
@@ -8222,7 +8308,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
if (insn & (1 << 20)) {
/* Load. */
tmp = tcg_temp_new_i32();
- tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, IS_USER(s));
if (i == 15) {
gen_bx(s, tmp);
} else if (i == rn) {
@@ -8234,7 +8320,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
} else {
/* Store. */
tmp = load_reg(s, i);
- tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, IS_USER(s));
tcg_temp_free_i32(tmp);
}
tcg_gen_addi_i32(addr, addr, 4);
@@ -9010,19 +9096,19 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
tmp = tcg_temp_new_i32();
switch (op) {
case 0:
- tcg_gen_qemu_ld8u(tmp, addr, user);
+ gen_aa32_ld8u(tmp, addr, user);
break;
case 4:
- tcg_gen_qemu_ld8s(tmp, addr, user);
+ gen_aa32_ld8s(tmp, addr, user);
break;
case 1:
- tcg_gen_qemu_ld16u(tmp, addr, user);
+ gen_aa32_ld16u(tmp, addr, user);
break;
case 5:
- tcg_gen_qemu_ld16s(tmp, addr, user);
+ gen_aa32_ld16s(tmp, addr, user);
break;
case 2:
- tcg_gen_qemu_ld32u(tmp, addr, user);
+ gen_aa32_ld32u(tmp, addr, user);
break;
default:
tcg_temp_free_i32(tmp);
@@ -9039,13 +9125,13 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
tmp = load_reg(s, rs);
switch (op) {
case 0:
- tcg_gen_qemu_st8(tmp, addr, user);
+ gen_aa32_st8(tmp, addr, user);
break;
case 1:
- tcg_gen_qemu_st16(tmp, addr, user);
+ gen_aa32_st16(tmp, addr, user);
break;
case 2:
- tcg_gen_qemu_st32(tmp, addr, user);
+ gen_aa32_st32(tmp, addr, user);
break;
default:
tcg_temp_free_i32(tmp);
@@ -9182,7 +9268,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
addr = tcg_temp_new_i32();
tcg_gen_movi_i32(addr, val);
tmp = tcg_temp_new_i32();
- tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, IS_USER(s));
tcg_temp_free_i32(addr);
store_reg(s, rd, tmp);
break;
@@ -9385,28 +9471,28 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
switch (op) {
case 0: /* str */
- tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, IS_USER(s));
break;
case 1: /* strh */
- tcg_gen_qemu_st16(tmp, addr, IS_USER(s));
+ gen_aa32_st16(tmp, addr, IS_USER(s));
break;
case 2: /* strb */
- tcg_gen_qemu_st8(tmp, addr, IS_USER(s));
+ gen_aa32_st8(tmp, addr, IS_USER(s));
break;
case 3: /* ldrsb */
- tcg_gen_qemu_ld8s(tmp, addr, IS_USER(s));
+ gen_aa32_ld8s(tmp, addr, IS_USER(s));
break;
case 4: /* ldr */
- tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, IS_USER(s));
break;
case 5: /* ldrh */
- tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
+ gen_aa32_ld16u(tmp, addr, IS_USER(s));
break;
case 6: /* ldrb */
- tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
+ gen_aa32_ld8u(tmp, addr, IS_USER(s));
break;
case 7: /* ldrsh */
- tcg_gen_qemu_ld16s(tmp, addr, IS_USER(s));
+ gen_aa32_ld16s(tmp, addr, IS_USER(s));
break;
}
if (op >= 3) { /* load */
@@ -9428,12 +9514,12 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
if (insn & (1 << 11)) {
/* load */
tmp = tcg_temp_new_i32();
- tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, IS_USER(s));
store_reg(s, rd, tmp);
} else {
/* store */
tmp = load_reg(s, rd);
- tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, IS_USER(s));
tcg_temp_free_i32(tmp);
}
tcg_temp_free_i32(addr);
@@ -9450,12 +9536,12 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
if (insn & (1 << 11)) {
/* load */
tmp = tcg_temp_new_i32();
- tcg_gen_qemu_ld8u(tmp, addr, IS_USER(s));
+ gen_aa32_ld8u(tmp, addr, IS_USER(s));
store_reg(s, rd, tmp);
} else {
/* store */
tmp = load_reg(s, rd);
- tcg_gen_qemu_st8(tmp, addr, IS_USER(s));
+ gen_aa32_st8(tmp, addr, IS_USER(s));
tcg_temp_free_i32(tmp);
}
tcg_temp_free_i32(addr);
@@ -9472,12 +9558,12 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
if (insn & (1 << 11)) {
/* load */
tmp = tcg_temp_new_i32();
- tcg_gen_qemu_ld16u(tmp, addr, IS_USER(s));
+ gen_aa32_ld16u(tmp, addr, IS_USER(s));
store_reg(s, rd, tmp);
} else {
/* store */
tmp = load_reg(s, rd);
- tcg_gen_qemu_st16(tmp, addr, IS_USER(s));
+ gen_aa32_st16(tmp, addr, IS_USER(s));
tcg_temp_free_i32(tmp);
}
tcg_temp_free_i32(addr);
@@ -9493,12 +9579,12 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
if (insn & (1 << 11)) {
/* load */
tmp = tcg_temp_new_i32();
- tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, IS_USER(s));
store_reg(s, rd, tmp);
} else {
/* store */
tmp = load_reg(s, rd);
- tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, IS_USER(s));
tcg_temp_free_i32(tmp);
}
tcg_temp_free_i32(addr);
@@ -9566,12 +9652,12 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
if (insn & (1 << 11)) {
/* pop */
tmp = tcg_temp_new_i32();
- tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, IS_USER(s));
store_reg(s, i, tmp);
} else {
/* push */
tmp = load_reg(s, i);
- tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, IS_USER(s));
tcg_temp_free_i32(tmp);
}
/* advance to the next address. */
@@ -9583,13 +9669,13 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
if (insn & (1 << 11)) {
/* pop pc */
tmp = tcg_temp_new_i32();
- tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, IS_USER(s));
/* don't set the pc until the rest of the instruction
has completed */
} else {
/* push lr */
tmp = load_reg(s, 14);
- tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, IS_USER(s));
tcg_temp_free_i32(tmp);
}
tcg_gen_addi_i32(addr, addr, 4);
@@ -9714,7 +9800,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
if (insn & (1 << 11)) {
/* load */
tmp = tcg_temp_new_i32();
- tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, IS_USER(s));
if (i == rn) {
loaded_var = tmp;
} else {
@@ -9723,7 +9809,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
} else {
/* store */
tmp = load_reg(s, i);
- tcg_gen_qemu_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, IS_USER(s));
tcg_temp_free_i32(tmp);
}
/* advance to the next address */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH v5 02/21] target-arm: Extract the disas struct to a header file
2013-07-01 17:34 [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 01/21] target-arm: Abstract out load/store from a vaddr in AArch32 Peter Maydell
@ 2013-07-01 17:35 ` Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 03/21] target-arm: Export cpu_env Peter Maydell
` (20 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Peter Maydell @ 2013-07-01 17:35 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Schwab, Alexander Graf, Mian M. Hamayun, patches
From: Alexander Graf <agraf@suse.de>
We will need to share the disassembly status struct between AArch32 and
AArch64 modes. So put it into a header file that both sides can use.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Message-id: 1368505980-17151-2-git-send-email-john.rigby@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/translate.c | 24 +-----------------------
target-arm/translate.h | 27 +++++++++++++++++++++++++++
2 files changed, 28 insertions(+), 23 deletions(-)
create mode 100644 target-arm/translate.h
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 1618524..1a9c1a0 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -45,29 +45,7 @@
#define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)
-/* internal defines */
-typedef struct DisasContext {
- target_ulong pc;
- int is_jmp;
- /* Nonzero if this instruction has been conditionally skipped. */
- int condjmp;
- /* The label that will be jumped to when the instruction is skipped. */
- int condlabel;
- /* Thumb-2 conditional execution bits. */
- int condexec_mask;
- int condexec_cond;
- struct TranslationBlock *tb;
- int singlestep_enabled;
- int thumb;
- int bswap_code;
-#if !defined(CONFIG_USER_ONLY)
- int user;
-#endif
- int vfp_enabled;
- int vec_len;
- int vec_stride;
-} DisasContext;
-
+#include "translate.h"
static uint32_t gen_opc_condexec_bits[OPC_BUF_SIZE];
#if defined(CONFIG_USER_ONLY)
diff --git a/target-arm/translate.h b/target-arm/translate.h
new file mode 100644
index 0000000..e727bc6
--- /dev/null
+++ b/target-arm/translate.h
@@ -0,0 +1,27 @@
+#ifndef TARGET_ARM_TRANSLATE_H
+#define TARGET_ARM_TRANSLATE_H
+
+/* internal defines */
+typedef struct DisasContext {
+ target_ulong pc;
+ int is_jmp;
+ /* Nonzero if this instruction has been conditionally skipped. */
+ int condjmp;
+ /* The label that will be jumped to when the instruction is skipped. */
+ int condlabel;
+ /* Thumb-2 conditional execution bits. */
+ int condexec_mask;
+ int condexec_cond;
+ struct TranslationBlock *tb;
+ int singlestep_enabled;
+ int thumb;
+ int bswap_code;
+#if !defined(CONFIG_USER_ONLY)
+ int user;
+#endif
+ int vfp_enabled;
+ int vec_len;
+ int vec_stride;
+} DisasContext;
+
+#endif /* TARGET_ARM_TRANSLATE_H */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH v5 03/21] target-arm: Export cpu_env
2013-07-01 17:34 [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 01/21] target-arm: Abstract out load/store from a vaddr in AArch32 Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 02/21] target-arm: Extract the disas struct to a header file Peter Maydell
@ 2013-07-01 17:35 ` Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 04/21] target-arm: Fix target_ulong/uint32_t confusions Peter Maydell
` (19 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Peter Maydell @ 2013-07-01 17:35 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Schwab, Alexander Graf, Mian M. Hamayun, patches
From: Alexander Graf <agraf@suse.de>
The cpu_env tcg variable will be used by both the AArch32 and AArch64
handling code. Unstaticify it, so that both sides can make use of it.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Message-id: 1368505980-17151-3-git-send-email-john.rigby@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/translate.c | 2 +-
target-arm/translate.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 1a9c1a0..a6c2cf9 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -59,7 +59,7 @@ static uint32_t gen_opc_condexec_bits[OPC_BUF_SIZE];
#define DISAS_WFI 4
#define DISAS_SWI 5
-static TCGv_ptr cpu_env;
+TCGv_ptr cpu_env;
/* We reuse the same 64-bit temporaries for efficiency. */
static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
static TCGv_i32 cpu_R[16];
diff --git a/target-arm/translate.h b/target-arm/translate.h
index e727bc6..8ba1433 100644
--- a/target-arm/translate.h
+++ b/target-arm/translate.h
@@ -24,4 +24,6 @@ typedef struct DisasContext {
int vec_stride;
} DisasContext;
+extern TCGv_ptr cpu_env;
+
#endif /* TARGET_ARM_TRANSLATE_H */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH v5 04/21] target-arm: Fix target_ulong/uint32_t confusions
2013-07-01 17:34 [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset Peter Maydell
` (2 preceding siblings ...)
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 03/21] target-arm: Export cpu_env Peter Maydell
@ 2013-07-01 17:35 ` Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 05/21] target-arm: Pass DisasContext* to gen_set_pc_im() Peter Maydell
` (18 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Peter Maydell @ 2013-07-01 17:35 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Schwab, Alexander Graf, Mian M. Hamayun, patches
From: Alexander Graf <agraf@suse.de>
Correct a few places that were using uint32_t or a 32 bit
only format string to handle something that should be a target_ulong.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: John Rigby <john.rigby@linaro.org>
[PMM: split out to separate patch; added gen_goto_tb() and
gen_set_pc_im() dest params to list of things to change.]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu.h | 4 ++--
target-arm/translate.c | 9 +++++----
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index abcc0b4..1f3beac 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -816,7 +816,7 @@ static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb)
}
/* Load an instruction and return it in the standard little-endian order */
-static inline uint32_t arm_ldl_code(CPUARMState *env, uint32_t addr,
+static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr,
bool do_swap)
{
uint32_t insn = cpu_ldl_code(env, addr);
@@ -827,7 +827,7 @@ static inline uint32_t arm_ldl_code(CPUARMState *env, uint32_t addr,
}
/* Ditto, for a halfword (Thumb) instruction */
-static inline uint16_t arm_lduw_code(CPUARMState *env, uint32_t addr,
+static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,
bool do_swap)
{
uint16_t insn = cpu_lduw_code(env, addr);
diff --git a/target-arm/translate.c b/target-arm/translate.c
index a6c2cf9..02319b3 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -903,7 +903,7 @@ DO_GEN_ST(st8)
DO_GEN_ST(st16)
DO_GEN_ST(st32)
-static inline void gen_set_pc_im(uint32_t val)
+static inline void gen_set_pc_im(target_ulong val)
{
tcg_gen_movi_i32(cpu_R[15], val);
}
@@ -3411,7 +3411,7 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
return 0;
}
-static inline void gen_goto_tb(DisasContext *s, int n, uint32_t dest)
+static inline void gen_goto_tb(DisasContext *s, int n, target_ulong dest)
{
TranslationBlock *tb;
@@ -9869,7 +9869,7 @@ static inline void gen_intermediate_code_internal(CPUARMState *env,
uint16_t *gen_opc_end;
int j, lj;
target_ulong pc_start;
- uint32_t next_page_start;
+ target_ulong next_page_start;
int num_insns;
int max_insns;
@@ -10023,7 +10023,8 @@ static inline void gen_intermediate_code_internal(CPUARMState *env,
}
if (tcg_check_temp_count()) {
- fprintf(stderr, "TCG temporary leak before %08x\n", dc->pc);
+ fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n",
+ dc->pc);
}
/* Translation stops when a conditional branch is encountered.
--
1.7.9.5
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH v5 05/21] target-arm: Pass DisasContext* to gen_set_pc_im()
2013-07-01 17:34 [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset Peter Maydell
` (3 preceding siblings ...)
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 04/21] target-arm: Fix target_ulong/uint32_t confusions Peter Maydell
@ 2013-07-01 17:35 ` Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 06/21] target-arm: Prepare translation for AArch64 code Peter Maydell
` (17 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Peter Maydell @ 2013-07-01 17:35 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Schwab, Alexander Graf, Mian M. Hamayun, patches
We want gen_set_pc_im() to work for both AArch64 and AArch32, but
to do this we'll need the DisasContext* so we can tell which mode
we're in, so pass it in as a parameter.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/translate.c | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 02319b3..c87a1f8 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -903,7 +903,7 @@ DO_GEN_ST(st8)
DO_GEN_ST(st16)
DO_GEN_ST(st32)
-static inline void gen_set_pc_im(target_ulong val)
+static inline void gen_set_pc_im(DisasContext *s, target_ulong val)
{
tcg_gen_movi_i32(cpu_R[15], val);
}
@@ -3418,10 +3418,10 @@ static inline void gen_goto_tb(DisasContext *s, int n, target_ulong dest)
tb = s->tb;
if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
tcg_gen_goto_tb(n);
- gen_set_pc_im(dest);
+ gen_set_pc_im(s, dest);
tcg_gen_exit_tb((tcg_target_long)tb + n);
} else {
- gen_set_pc_im(dest);
+ gen_set_pc_im(s, dest);
tcg_gen_exit_tb(0);
}
}
@@ -3550,7 +3550,7 @@ gen_set_condexec (DisasContext *s)
static void gen_exception_insn(DisasContext *s, int offset, int excp)
{
gen_set_condexec(s);
- gen_set_pc_im(s->pc - offset);
+ gen_set_pc_im(s, s->pc - offset);
gen_exception(excp);
s->is_jmp = DISAS_JUMP;
}
@@ -3559,7 +3559,7 @@ static void gen_nop_hint(DisasContext *s, int val)
{
switch (val) {
case 3: /* wfi */
- gen_set_pc_im(s->pc);
+ gen_set_pc_im(s, s->pc);
s->is_jmp = DISAS_WFI;
break;
case 2: /* wfe */
@@ -6335,7 +6335,7 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
if (isread) {
return 1;
}
- gen_set_pc_im(s->pc);
+ gen_set_pc_im(s, s->pc);
s->is_jmp = DISAS_WFI;
return 0;
default:
@@ -6351,7 +6351,7 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
tmp64 = tcg_const_i64(ri->resetvalue);
} else if (ri->readfn) {
TCGv_ptr tmpptr;
- gen_set_pc_im(s->pc);
+ gen_set_pc_im(s, s->pc);
tmp64 = tcg_temp_new_i64();
tmpptr = tcg_const_ptr(ri);
gen_helper_get_cp_reg64(tmp64, cpu_env, tmpptr);
@@ -6374,7 +6374,7 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
tmp = tcg_const_i32(ri->resetvalue);
} else if (ri->readfn) {
TCGv_ptr tmpptr;
- gen_set_pc_im(s->pc);
+ gen_set_pc_im(s, s->pc);
tmp = tcg_temp_new_i32();
tmpptr = tcg_const_ptr(ri);
gen_helper_get_cp_reg(tmp, cpu_env, tmpptr);
@@ -6409,7 +6409,7 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
tcg_temp_free_i32(tmphi);
if (ri->writefn) {
TCGv_ptr tmpptr = tcg_const_ptr(ri);
- gen_set_pc_im(s->pc);
+ gen_set_pc_im(s, s->pc);
gen_helper_set_cp_reg64(cpu_env, tmpptr, tmp64);
tcg_temp_free_ptr(tmpptr);
} else {
@@ -6420,7 +6420,7 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
if (ri->writefn) {
TCGv_i32 tmp;
TCGv_ptr tmpptr;
- gen_set_pc_im(s->pc);
+ gen_set_pc_im(s, s->pc);
tmp = load_reg(s, rt);
tmpptr = tcg_const_ptr(ri);
gen_helper_set_cp_reg(cpu_env, tmpptr, tmp);
@@ -7964,7 +7964,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
break;
case 0xf:
/* swi */
- gen_set_pc_im(s->pc);
+ gen_set_pc_im(s, s->pc);
s->is_jmp = DISAS_SWI;
break;
default:
@@ -9814,7 +9814,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
if (cond == 0xf) {
/* swi */
- gen_set_pc_im(s->pc);
+ gen_set_pc_im(s, s->pc);
s->is_jmp = DISAS_SWI;
break;
}
@@ -10062,7 +10062,7 @@ static inline void gen_intermediate_code_internal(CPUARMState *env,
gen_set_label(dc->condlabel);
}
if (dc->condjmp || !dc->is_jmp) {
- gen_set_pc_im(dc->pc);
+ gen_set_pc_im(dc, dc->pc);
dc->condjmp = 0;
}
gen_set_condexec(dc);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH v5 06/21] target-arm: Prepare translation for AArch64 code
2013-07-01 17:34 [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset Peter Maydell
` (4 preceding siblings ...)
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 05/21] target-arm: Pass DisasContext* to gen_set_pc_im() Peter Maydell
@ 2013-07-01 17:35 ` Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 07/21] target-arm: Add AArch64 translation stub Peter Maydell
` (16 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Peter Maydell @ 2013-07-01 17:35 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Schwab, Alexander Graf, Mian M. Hamayun, patches
From: Alexander Graf <agraf@suse.de>
This patch adds all the prerequisites for AArch64 support that didn't
fit into split up patches. It extends important bits in the core cpu
headers to also take AArch64 mode into account.
Add new ARM_TBFLAG_AARCH64_STATE translation buffer flag
indicate an ARMv8 cpu running in aarch64 mode vs aarch32 mode.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Message-id: 1368505980-17151-4-git-send-email-john.rigby@linaro.org
[PMM:
* rearranged tbflags so AArch64? is bit 31 and if it is set then
30..0 are freely available for whatever makes most sense for that mode
* added version bump since we change VFP migration state
* added a comment about how VFP/Neon register state works
* physical address space is 48 bits, not 64
* added ARM_FEATURE_AARCH64 flag to identify 64-bit capable CPUs
]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu.c | 8 +++
target-arm/cpu.h | 131 ++++++++++++++++++++++++++++++++++++++----------
target-arm/machine.c | 8 +--
target-arm/translate.c | 38 ++++++++++----
target-arm/translate.h | 1 +
5 files changed, 147 insertions(+), 39 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 1bc227e..0a8c8df 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -80,6 +80,11 @@ static void arm_cpu_reset(CPUState *s)
env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
}
+ if (arm_feature(env, ARM_FEATURE_AARCH64)) {
+ /* 64 bit CPUs always start in 64 bit mode */
+ env->aarch64 = 1;
+ }
+
#if defined(CONFIG_USER_ONLY)
env->uncached_cpsr = ARM_CPU_MODE_USR;
/* For user mode we must enable access to coprocessors */
@@ -756,6 +761,9 @@ static void arm_any_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
set_feature(&cpu->env, ARM_FEATURE_V7MP);
+#ifdef TARGET_AARCH64
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+#endif
cpu->midr = 0xffffffff;
}
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 1f3beac..78614a4 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -19,13 +19,19 @@
#ifndef CPU_ARM_H
#define CPU_ARM_H
-#define TARGET_LONG_BITS 32
+#include "config.h"
-#define ELF_MACHINE EM_ARM
+#if defined(TARGET_AARCH64)
+ /* AArch64 definitions */
+# define TARGET_LONG_BITS 64
+# define ELF_MACHINE EM_AARCH64
+#else
+# define TARGET_LONG_BITS 32
+# define ELF_MACHINE EM_ARM
+#endif
#define CPUArchState struct CPUARMState
-#include "config.h"
#include "qemu-common.h"
#include "exec/cpu-defs.h"
@@ -79,6 +85,20 @@ struct arm_boot_info;
typedef struct CPUARMState {
/* Regs for current mode. */
uint32_t regs[16];
+
+ /* 32/64 switch only happens when taking and returning from
+ * exceptions so the overlap semantics are taken care of then
+ * instead of having a complicated union.
+ */
+ /* Regs for A64 mode. */
+ uint64_t xregs[32];
+ uint64_t pc;
+ /* TODO: pstate doesn't correspond to an architectural register;
+ * it would be better modelled as the underlying fields.
+ */
+ uint32_t pstate;
+ uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */
+
/* Frequently accessed CPSR bits are stored separately for efficiency.
This contains all the other bits. Use cpsr_{read,write} to access
the whole CPSR. */
@@ -154,6 +174,11 @@ typedef struct CPUARMState {
uint32_t c15_power_control; /* power control */
} cp15;
+ /* System registers (AArch64) */
+ struct {
+ uint64_t tpidr_el0;
+ } sr;
+
struct {
uint32_t other_sp;
uint32_t vecbase;
@@ -170,7 +195,22 @@ typedef struct CPUARMState {
/* VFP coprocessor state. */
struct {
- float64 regs[32];
+ /* VFP/Neon register state. Note that the mapping between S, D and Q
+ * views of the register bank differs between AArch64 and AArch32:
+ * In AArch32:
+ * Qn = regs[2n+1]:regs[2n]
+ * Dn = regs[n]
+ * Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n
+ * (and regs[32] to regs[63] are inaccessible)
+ * In AArch64:
+ * Qn = regs[2n+1]:regs[2n]
+ * Dn = regs[2n]
+ * Sn = regs[2n] bits 31..0
+ * This corresponds to the architecturally defined mapping between
+ * the two execution states, and means we do not need to explicitly
+ * map these registers when changing states.
+ */
+ float64 regs[64];
uint32_t xregs[16];
/* We store these fpcsr fields separately for convenience. */
@@ -240,6 +280,20 @@ int bank_number(int mode);
void switch_mode(CPUARMState *, int);
uint32_t do_arm_semihosting(CPUARMState *env);
+static inline bool is_a64(CPUARMState *env)
+{
+ return env->aarch64;
+}
+
+#define PSTATE_N_SHIFT 3
+#define PSTATE_N (1 << PSTATE_N_SHIFT)
+#define PSTATE_Z_SHIFT 2
+#define PSTATE_Z (1 << PSTATE_Z_SHIFT)
+#define PSTATE_C_SHIFT 1
+#define PSTATE_C (1 << PSTATE_C_SHIFT)
+#define PSTATE_V_SHIFT 0
+#define PSTATE_V (1 << PSTATE_V_SHIFT)
+
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
is returned if the signal was handled by the virtual CPU. */
@@ -392,6 +446,7 @@ enum arm_features {
ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
+ ARM_FEATURE_AARCH64, /* supports 64 bit mode */
};
static inline int arm_feature(CPUARMState *env, int feature)
@@ -708,8 +763,13 @@ bool write_cpustate_to_list(ARMCPU *cpu);
#define TARGET_PAGE_BITS 10
#endif
-#define TARGET_PHYS_ADDR_SPACE_BITS 40
-#define TARGET_VIRT_ADDR_SPACE_BITS 32
+#if defined(TARGET_AARCH64)
+# define TARGET_PHYS_ADDR_SPACE_BITS 48
+# define TARGET_VIRT_ADDR_SPACE_BITS 64
+#else
+# define TARGET_PHYS_ADDR_SPACE_BITS 40
+# define TARGET_VIRT_ADDR_SPACE_BITS 32
+#endif
static inline CPUARMState *cpu_init(const char *cpu_model)
{
@@ -745,7 +805,13 @@ static inline void cpu_clone_regs(CPUARMState *env, target_ulong newsp)
#include "exec/cpu-all.h"
-/* Bit usage in the TB flags field: */
+/* Bit usage in the TB flags field: bit 31 indicates whether we are
+ * in 32 or 64 bit mode. The meaning of the other bits depends on that.
+ */
+#define ARM_TBFLAG_AARCH64_STATE_SHIFT 31
+#define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT)
+
+/* Bit usage when in AArch32 state: */
#define ARM_TBFLAG_THUMB_SHIFT 0
#define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT)
#define ARM_TBFLAG_VECLEN_SHIFT 1
@@ -760,9 +826,12 @@ static inline void cpu_clone_regs(CPUARMState *env, target_ulong newsp)
#define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
#define ARM_TBFLAG_BSWAP_CODE_SHIFT 16
#define ARM_TBFLAG_BSWAP_CODE_MASK (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT)
-/* Bits 31..17 are currently unused. */
+
+/* Bit usage when in AArch64 state: currently no bits defined */
/* some convenience accessor macros */
+#define ARM_TBFLAG_AARCH64_STATE(F) \
+ (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT)
#define ARM_TBFLAG_THUMB(F) \
(((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
#define ARM_TBFLAG_VECLEN(F) \
@@ -781,25 +850,31 @@ static inline void cpu_clone_regs(CPUARMState *env, target_ulong newsp)
static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
- int privmode;
- *pc = env->regs[15];
- *cs_base = 0;
- *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
- | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
- | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
- | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT)
- | (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT);
- if (arm_feature(env, ARM_FEATURE_M)) {
- privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
+ if (is_a64(env)) {
+ *pc = env->pc;
+ *flags = ARM_TBFLAG_AARCH64_STATE_MASK;
} else {
- privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
- }
- if (privmode) {
- *flags |= ARM_TBFLAG_PRIV_MASK;
- }
- if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
- *flags |= ARM_TBFLAG_VFPEN_MASK;
+ int privmode;
+ *pc = env->regs[15];
+ *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
+ | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
+ | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
+ | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT)
+ | (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT);
+ if (arm_feature(env, ARM_FEATURE_M)) {
+ privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
+ } else {
+ privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
+ }
+ if (privmode) {
+ *flags |= ARM_TBFLAG_PRIV_MASK;
+ }
+ if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
+ *flags |= ARM_TBFLAG_VFPEN_MASK;
+ }
}
+
+ *cs_base = 0;
}
static inline bool cpu_has_work(CPUState *cpu)
@@ -812,7 +887,11 @@ static inline bool cpu_has_work(CPUState *cpu)
static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb)
{
- env->regs[15] = tb->pc;
+ if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
+ env->pc = tb->pc;
+ } else {
+ env->regs[15] = tb->pc;
+ }
}
/* Load an instruction and return it in the standard little-endian order */
diff --git a/target-arm/machine.c b/target-arm/machine.c
index 6d4c2d4..722516f 100644
--- a/target-arm/machine.c
+++ b/target-arm/machine.c
@@ -37,11 +37,11 @@ static const VMStateInfo vmstate_fpscr = {
static const VMStateDescription vmstate_vfp = {
.name = "cpu/vfp",
- .version_id = 2,
- .minimum_version_id = 2,
- .minimum_version_id_old = 2,
+ .version_id = 3,
+ .minimum_version_id = 3,
+ .minimum_version_id_old = 3,
.fields = (VMStateField[]) {
- VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 32),
+ VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 64),
/* The xregs array is a little awkward because element 1 (FPSCR)
* requires a specific accessor, so we have to split it up in
* the vmstate:
diff --git a/target-arm/translate.c b/target-arm/translate.c
index c87a1f8..2935cea 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -9884,16 +9884,32 @@ static inline void gen_intermediate_code_internal(CPUARMState *env,
dc->pc = pc_start;
dc->singlestep_enabled = env->singlestep_enabled;
dc->condjmp = 0;
- dc->thumb = ARM_TBFLAG_THUMB(tb->flags);
- dc->bswap_code = ARM_TBFLAG_BSWAP_CODE(tb->flags);
- dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1;
- dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4;
+
+ if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
+ dc->aarch64 = 1;
+ dc->thumb = 0;
+ dc->bswap_code = 0;
+ dc->condexec_mask = 0;
+ dc->condexec_cond = 0;
+#if !defined(CONFIG_USER_ONLY)
+ dc->user = 0;
+#endif
+ dc->vfp_enabled = 0;
+ dc->vec_len = 0;
+ dc->vec_stride = 0;
+ } else {
+ dc->aarch64 = 0;
+ dc->thumb = ARM_TBFLAG_THUMB(tb->flags);
+ dc->bswap_code = ARM_TBFLAG_BSWAP_CODE(tb->flags);
+ dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1;
+ dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4;
#if !defined(CONFIG_USER_ONLY)
- dc->user = (ARM_TBFLAG_PRIV(tb->flags) == 0);
+ dc->user = (ARM_TBFLAG_PRIV(tb->flags) == 0);
#endif
- dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags);
- dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags);
- dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);
+ dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags);
+ dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags);
+ dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);
+ }
cpu_F0s = tcg_temp_new_i32();
cpu_F1s = tcg_temp_new_i32();
cpu_F0d = tcg_temp_new_i64();
@@ -10196,6 +10212,10 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
void restore_state_to_opc(CPUARMState *env, TranslationBlock *tb, int pc_pos)
{
- env->regs[15] = tcg_ctx.gen_opc_pc[pc_pos];
+ if (is_a64(env)) {
+ env->pc = tcg_ctx.gen_opc_pc[pc_pos];
+ } else {
+ env->regs[15] = tcg_ctx.gen_opc_pc[pc_pos];
+ }
env->condexec_bits = gen_opc_condexec_bits[pc_pos];
}
diff --git a/target-arm/translate.h b/target-arm/translate.h
index 8ba1433..5be2eed 100644
--- a/target-arm/translate.h
+++ b/target-arm/translate.h
@@ -22,6 +22,7 @@ typedef struct DisasContext {
int vfp_enabled;
int vec_len;
int vec_stride;
+ int aarch64;
} DisasContext;
extern TCGv_ptr cpu_env;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH v5 07/21] target-arm: Add AArch64 translation stub
2013-07-01 17:34 [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset Peter Maydell
` (5 preceding siblings ...)
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 06/21] target-arm: Prepare translation for AArch64 code Peter Maydell
@ 2013-07-01 17:35 ` Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 08/21] gdbstub: Add AArch64 support Peter Maydell
` (15 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Peter Maydell @ 2013-07-01 17:35 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Schwab, Alexander Graf, Mian M. Hamayun, patches
From: Alexander Graf <agraf@suse.de>
We should translate AArch64 mode separately from AArch32 mode. In AArch64 mode,
registers look vastly different, instruction encoding is completely different,
basically the system turns into a different machine.
So let's do a simple if() in translate.c to decide whether we can handle the
current code in the legacy AArch32 code or in the new AArch64 code.
So far, the translation always complains about unallocated instructions. There
is no emulator functionality in this patch!
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Message-id: 1368505980-17151-5-git-send-email-john.rigby@linaro.org
[PMM:
* provide no-op versions of a64 functions ifndef TARGET_AARCH64;
this lets us avoid #ifdefs in translate.c
* insert the missing call to disas_a64_insn()
]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/Makefile.objs | 1 +
target-arm/translate-a64.c | 137 ++++++++++++++++++++++++++++++++++++++++++++
target-arm/translate.c | 19 +++++-
target-arm/translate.h | 25 ++++++++
4 files changed, 179 insertions(+), 3 deletions(-)
create mode 100644 target-arm/translate-a64.c
diff --git a/target-arm/Makefile.objs b/target-arm/Makefile.objs
index 4a6e52e..3378eb8 100644
--- a/target-arm/Makefile.objs
+++ b/target-arm/Makefile.objs
@@ -4,3 +4,4 @@ obj-$(CONFIG_KVM) += kvm.o
obj-$(CONFIG_NO_KVM) += kvm-stub.o
obj-y += translate.o op_helper.o helper.o cpu.o
obj-y += neon_helper.o iwmmxt_helper.o
+obj-$(TARGET_AARCH64) += translate-a64.o
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
new file mode 100644
index 0000000..29e8937
--- /dev/null
+++ b/target-arm/translate-a64.c
@@ -0,0 +1,137 @@
+/*
+ * AArch64 translation
+ *
+ * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+#include <stdarg.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <inttypes.h>
+
+#include "cpu.h"
+#include "tcg-op.h"
+#include "qemu/log.h"
+#include "translate.h"
+#include "qemu/host-utils.h"
+
+#include "helper.h"
+#define GEN_HELPER 1
+#include "helper.h"
+
+static TCGv_i64 cpu_X[32];
+static TCGv_i64 cpu_pc;
+static TCGv_i32 pstate;
+
+static const char *regnames[] = {
+ "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
+ "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
+ "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
+ "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
+};
+
+/* initialize TCG globals. */
+void a64_translate_init(void)
+{
+ int i;
+
+ cpu_pc = tcg_global_mem_new_i64(TCG_AREG0,
+ offsetof(CPUARMState, pc),
+ "pc");
+ for (i = 0; i < 32; i++) {
+ cpu_X[i] = tcg_global_mem_new_i64(TCG_AREG0,
+ offsetof(CPUARMState, xregs[i]),
+ regnames[i]);
+ }
+
+ pstate = tcg_global_mem_new_i32(TCG_AREG0,
+ offsetof(CPUARMState, pstate),
+ "pstate");
+}
+
+void cpu_dump_state_a64(CPUARMState *env, FILE *f, fprintf_function cpu_fprintf,
+ int flags)
+{
+ int i;
+
+ cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n",
+ env->pc, env->xregs[31]);
+ for (i = 0; i < 31; i++) {
+ cpu_fprintf(f, "X%02d=%016"PRIx64, i, env->xregs[i]);
+ if ((i % 4) == 3) {
+ cpu_fprintf(f, "\n");
+ } else {
+ cpu_fprintf(f, " ");
+ }
+ }
+ cpu_fprintf(f, "PSTATE=%c%c%c%c\n",
+ env->pstate & PSTATE_N ? 'n' : '.',
+ env->pstate & PSTATE_Z ? 'z' : '.',
+ env->pstate & PSTATE_C ? 'c' : '.',
+ env->pstate & PSTATE_V ? 'v' : '.');
+ cpu_fprintf(f, "\n");
+}
+
+void gen_a64_set_pc_im(uint64_t val)
+{
+ tcg_gen_movi_i64(cpu_pc, val);
+}
+
+static void gen_exception(int excp)
+{
+ TCGv_i32 tmp = tcg_temp_new_i32();
+ tcg_gen_movi_i32(tmp, excp);
+ gen_helper_exception(cpu_env, tmp);
+ tcg_temp_free_i32(tmp);
+}
+
+static void gen_exception_insn(DisasContext *s, int offset, int excp)
+{
+ gen_a64_set_pc_im(s->pc - offset);
+ gen_exception(excp);
+ s->is_jmp = DISAS_JUMP;
+}
+
+static void real_unallocated_encoding(DisasContext *s)
+{
+ fprintf(stderr, "Unknown instruction: %#x\n",
+ arm_ldl_code(cpu_single_env, s->pc - 4, s->bswap_code));
+ gen_exception_insn(s, 4, EXCP_UDEF);
+}
+
+#define unallocated_encoding(s) do { \
+ fprintf(stderr, "unallocated encoding at line: %d\n", __LINE__); \
+ real_unallocated_encoding(s); \
+ } while (0)
+
+void disas_a64_insn(CPUARMState *env, DisasContext *s)
+{
+ uint32_t insn;
+
+ insn = arm_ldl_code(env, s->pc, s->bswap_code);
+ s->pc += 4;
+
+ switch ((insn >> 24) & 0x1f) {
+ default:
+ unallocated_encoding(s);
+ break;
+ }
+
+ if (unlikely(s->singlestep_enabled) && (s->is_jmp == DISAS_TB_JUMP)) {
+ /* go through the main loop for single step */
+ s->is_jmp = DISAS_JUMP;
+ }
+}
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 2935cea..93fcc8d 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -112,6 +112,8 @@ void arm_translate_init(void)
offsetof(CPUARMState, exclusive_info), "exclusive_info");
#endif
+ a64_translate_init();
+
#define GEN_HELPER 2
#include "helper.h"
}
@@ -905,7 +907,11 @@ DO_GEN_ST(st32)
static inline void gen_set_pc_im(DisasContext *s, target_ulong val)
{
- tcg_gen_movi_i32(cpu_R[15], val);
+ if (s->aarch64) {
+ gen_a64_set_pc_im(val);
+ } else {
+ tcg_gen_movi_i32(cpu_R[15], val);
+ }
}
/* Force a TB lookup after an instruction that changes the CPU state. */
@@ -9971,7 +9977,7 @@ static inline void gen_intermediate_code_internal(CPUARMState *env,
do {
#ifdef CONFIG_USER_ONLY
/* Intercept jump to the magic kernel page. */
- if (dc->pc >= 0xffff0000) {
+ if (!dc->aarch64 && dc->pc >= 0xffff0000) {
/* We always get here via a jump, so know we are not in a
conditional execution block. */
gen_exception(EXCP_KERNEL_TRAP);
@@ -10019,7 +10025,9 @@ static inline void gen_intermediate_code_internal(CPUARMState *env,
tcg_gen_debug_insn_start(dc->pc);
}
- if (dc->thumb) {
+ if (dc->aarch64) {
+ disas_a64_insn(env, dc);
+ } else if (dc->thumb) {
disas_thumb_insn(env, dc);
if (dc->condexec_mask) {
dc->condexec_cond = (dc->condexec_cond & 0xe)
@@ -10174,6 +10182,11 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
int i;
uint32_t psr;
+ if (is_a64(env)) {
+ cpu_dump_state_a64(env, f, cpu_fprintf, flags);
+ return;
+ }
+
for(i=0;i<16;i++) {
cpu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
if ((i % 4) == 3)
diff --git a/target-arm/translate.h b/target-arm/translate.h
index 5be2eed..79aa715 100644
--- a/target-arm/translate.h
+++ b/target-arm/translate.h
@@ -27,4 +27,29 @@ typedef struct DisasContext {
extern TCGv_ptr cpu_env;
+#ifdef TARGET_AARCH64
+void a64_translate_init(void);
+void cpu_dump_state_a64(CPUARMState *env, FILE *f,
+ fprintf_function cpu_fprintf, int flags);
+void disas_a64_insn(CPUARMState *env, DisasContext *s);
+void gen_a64_set_pc_im(uint64_t val);
+#else
+static inline void a64_translate_init(void)
+{
+}
+
+static inline void cpu_dump_state_a64(CPUARMState *env, FILE *f,
+ fprintf_function cpu_fprintf, int flags)
+{
+}
+
+static inline void disas_a64_insn(CPUARMState *env, DisasContext *s)
+{
+}
+
+static inline void gen_a64_set_pc_im(uint64_t val)
+{
+}
+#endif
+
#endif /* TARGET_ARM_TRANSLATE_H */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH v5 08/21] gdbstub: Add AArch64 support
2013-07-01 17:34 [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset Peter Maydell
` (6 preceding siblings ...)
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 07/21] target-arm: Add AArch64 translation stub Peter Maydell
@ 2013-07-01 17:35 ` Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 09/21] linux-user: Don't treat AArch64 cpu names specially Peter Maydell
` (14 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Peter Maydell @ 2013-07-01 17:35 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Schwab, Alexander Graf, Mian M. Hamayun, patches
From: Alexander Graf <agraf@suse.de>
We want to be able to debug AArch64 guests. So let's add the respective gdb
stub functions and xml descriptions that allow us to do so.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Message-id: 1368505980-17151-6-git-send-email-john.rigby@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
gdb-xml/aarch64-core.xml | 46 +++++++++++++++++++++++++
gdb-xml/aarch64-fpu.xml | 86 ++++++++++++++++++++++++++++++++++++++++++++++
gdbstub.c | 53 ++++++++++++++++++++++++++++
3 files changed, 185 insertions(+)
create mode 100644 gdb-xml/aarch64-core.xml
create mode 100644 gdb-xml/aarch64-fpu.xml
diff --git a/gdb-xml/aarch64-core.xml b/gdb-xml/aarch64-core.xml
new file mode 100644
index 0000000..e1e9dc3
--- /dev/null
+++ b/gdb-xml/aarch64-core.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2009-2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.aarch64.core">
+ <reg name="x0" bitsize="64"/>
+ <reg name="x1" bitsize="64"/>
+ <reg name="x2" bitsize="64"/>
+ <reg name="x3" bitsize="64"/>
+ <reg name="x4" bitsize="64"/>
+ <reg name="x5" bitsize="64"/>
+ <reg name="x6" bitsize="64"/>
+ <reg name="x7" bitsize="64"/>
+ <reg name="x8" bitsize="64"/>
+ <reg name="x9" bitsize="64"/>
+ <reg name="x10" bitsize="64"/>
+ <reg name="x11" bitsize="64"/>
+ <reg name="x12" bitsize="64"/>
+ <reg name="x13" bitsize="64"/>
+ <reg name="x14" bitsize="64"/>
+ <reg name="x15" bitsize="64"/>
+ <reg name="x16" bitsize="64"/>
+ <reg name="x17" bitsize="64"/>
+ <reg name="x18" bitsize="64"/>
+ <reg name="x19" bitsize="64"/>
+ <reg name="x20" bitsize="64"/>
+ <reg name="x21" bitsize="64"/>
+ <reg name="x22" bitsize="64"/>
+ <reg name="x23" bitsize="64"/>
+ <reg name="x24" bitsize="64"/>
+ <reg name="x25" bitsize="64"/>
+ <reg name="x26" bitsize="64"/>
+ <reg name="x27" bitsize="64"/>
+ <reg name="x28" bitsize="64"/>
+ <reg name="x29" bitsize="64"/>
+ <reg name="x30" bitsize="64"/>
+ <reg name="sp" bitsize="64" type="data_ptr"/>
+
+ <reg name="pc" bitsize="64" type="code_ptr"/>
+ <reg name="cpsr" bitsize="32"/>
+</feature>
diff --git a/gdb-xml/aarch64-fpu.xml b/gdb-xml/aarch64-fpu.xml
new file mode 100644
index 0000000..997197e
--- /dev/null
+++ b/gdb-xml/aarch64-fpu.xml
@@ -0,0 +1,86 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2009-2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.aarch64.fpu">
+ <vector id="v2d" type="ieee_double" count="2"/>
+ <vector id="v2u" type="uint64" count="2"/>
+ <vector id="v2i" type="int64" count="2"/>
+ <vector id="v4f" type="ieee_single" count="4"/>
+ <vector id="v4u" type="uint32" count="4"/>
+ <vector id="v4i" type="int32" count="4"/>
+ <vector id="v8u" type="uint16" count="8"/>
+ <vector id="v8i" type="int16" count="8"/>
+ <vector id="v16u" type="uint8" count="16"/>
+ <vector id="v16i" type="int8" count="16"/>
+ <vector id="v1u" type="uint128" count="1"/>
+ <vector id="v1i" type="int128" count="1"/>
+ <union id="vnd">
+ <field name="f" type="v2d"/>
+ <field name="u" type="v2u"/>
+ <field name="s" type="v2i"/>
+ </union>
+ <union id="vns">
+ <field name="f" type="v4f"/>
+ <field name="u" type="v4u"/>
+ <field name="s" type="v4i"/>
+ </union>
+ <union id="vnh">
+ <field name="u" type="v8u"/>
+ <field name="s" type="v8i"/>
+ </union>
+ <union id="vnb">
+ <field name="u" type="v16u"/>
+ <field name="s" type="v16i"/>
+ </union>
+ <union id="vnq">
+ <field name="u" type="v1u"/>
+ <field name="s" type="v1i"/>
+ </union>
+ <union id="aarch64v">
+ <field name="d" type="vnd"/>
+ <field name="s" type="vns"/>
+ <field name="h" type="vnh"/>
+ <field name="b" type="vnb"/>
+ <field name="q" type="vnq"/>
+ </union>
+ <reg name="v0" bitsize="128" type="aarch64v" regnum="34"/>
+ <reg name="v1" bitsize="128" type="aarch64v" />
+ <reg name="v2" bitsize="128" type="aarch64v" />
+ <reg name="v3" bitsize="128" type="aarch64v" />
+ <reg name="v4" bitsize="128" type="aarch64v" />
+ <reg name="v5" bitsize="128" type="aarch64v" />
+ <reg name="v6" bitsize="128" type="aarch64v" />
+ <reg name="v7" bitsize="128" type="aarch64v" />
+ <reg name="v8" bitsize="128" type="aarch64v" />
+ <reg name="v9" bitsize="128" type="aarch64v" />
+ <reg name="v10" bitsize="128" type="aarch64v"/>
+ <reg name="v11" bitsize="128" type="aarch64v"/>
+ <reg name="v12" bitsize="128" type="aarch64v"/>
+ <reg name="v13" bitsize="128" type="aarch64v"/>
+ <reg name="v14" bitsize="128" type="aarch64v"/>
+ <reg name="v15" bitsize="128" type="aarch64v"/>
+ <reg name="v16" bitsize="128" type="aarch64v"/>
+ <reg name="v17" bitsize="128" type="aarch64v"/>
+ <reg name="v18" bitsize="128" type="aarch64v"/>
+ <reg name="v19" bitsize="128" type="aarch64v"/>
+ <reg name="v20" bitsize="128" type="aarch64v"/>
+ <reg name="v21" bitsize="128" type="aarch64v"/>
+ <reg name="v22" bitsize="128" type="aarch64v"/>
+ <reg name="v23" bitsize="128" type="aarch64v"/>
+ <reg name="v24" bitsize="128" type="aarch64v"/>
+ <reg name="v25" bitsize="128" type="aarch64v"/>
+ <reg name="v26" bitsize="128" type="aarch64v"/>
+ <reg name="v27" bitsize="128" type="aarch64v"/>
+ <reg name="v28" bitsize="128" type="aarch64v"/>
+ <reg name="v29" bitsize="128" type="aarch64v"/>
+ <reg name="v30" bitsize="128" type="aarch64v"/>
+ <reg name="v31" bitsize="128" type="aarch64v"/>
+ <reg name="fpsr" bitsize="32"/>
+ <reg name="fpcr" bitsize="32"/>
+</feature>
diff --git a/gdbstub.c b/gdbstub.c
index 3101a43..757805d 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -940,6 +940,59 @@ static int cpu_gdb_write_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
return 8;
#endif
}
+#elif defined(TARGET_AARCH64)
+
+#define NUM_CORE_REGS 34
+#define GDB_CORE_XML "aarch64-core.xml"
+
+static int cpu_gdb_read_register(CPUARMState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 31) {
+ /* Core integer register. */
+ GET_REG64(env->xregs[n]);
+ }
+ switch (n) {
+ case 31:
+ GET_REG64(env->xregs[31]);
+ break;
+ case 32:
+ GET_REG64(env->pc);
+ break;
+ case 33:
+ GET_REG32(env->pstate);
+ break;
+ }
+ /* Unknown register. */
+ return 0;
+}
+
+static int cpu_gdb_write_register(CPUARMState *env, uint8_t *mem_buf, int n)
+{
+ uint64_t tmp;
+
+ tmp = ldq_p(mem_buf);
+
+ if (n < 31) {
+ /* Core integer register. */
+ env->xregs[n] = tmp;
+ return 8;
+ }
+ switch (n) {
+ case 31:
+ env->xregs[31] = tmp;
+ return 8;
+ case 32:
+ env->pc = tmp;
+ return 8;
+ case 33:
+ /* CPSR */
+ env->pstate = tmp;
+ return 4;
+ }
+ /* Unknown register. */
+ return 0;
+}
+
#elif defined (TARGET_ARM)
/* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect
--
1.7.9.5
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH v5 09/21] linux-user: Don't treat AArch64 cpu names specially
2013-07-01 17:34 [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset Peter Maydell
` (7 preceding siblings ...)
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 08/21] gdbstub: Add AArch64 support Peter Maydell
@ 2013-07-01 17:35 ` Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 10/21] linux-user: Add cpu loop for AArch64 Peter Maydell
` (13 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Peter Maydell @ 2013-07-01 17:35 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Schwab, Alexander Graf, Mian M. Hamayun, patches
From: Alexander Graf <agraf@suse.de>
32-bit ARM has a lot of different names for different types of CPUs it supports.
On AArch64, we don't have this, so we really don't want to execute the 32-bit
logic. Stub it out for AArch64 linux-user guests.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Message-id: 1368505980-17151-7-git-send-email-john.rigby@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
linux-user/cpu-uname.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/linux-user/cpu-uname.c b/linux-user/cpu-uname.c
index 59cd647..89bdb91 100644
--- a/linux-user/cpu-uname.c
+++ b/linux-user/cpu-uname.c
@@ -30,7 +30,8 @@
* return here */
const char *cpu_to_uname_machine(void *cpu_env)
{
-#ifdef TARGET_ARM
+#if defined(TARGET_ARM) && !defined(TARGET_AARCH64)
+
/* utsname machine name on linux arm is CPU arch name + endianness, e.g.
* armv7l; to get a list of CPU arch names from the linux source, use:
* grep arch_name: -A1 linux/arch/arm/mm/proc-*.S
--
1.7.9.5
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH v5 10/21] linux-user: Add cpu loop for AArch64
2013-07-01 17:34 [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset Peter Maydell
` (8 preceding siblings ...)
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 09/21] linux-user: Don't treat AArch64 cpu names specially Peter Maydell
@ 2013-07-01 17:35 ` Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 11/21] linux-user: Add syscall number definitions " Peter Maydell
` (12 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Peter Maydell @ 2013-07-01 17:35 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Schwab, Alexander Graf, Mian M. Hamayun, patches
Add the main linux-user cpu loop for AArch64. Since AArch64
has a different system call interface, doesn't need to worry
about FPA emulation and may in the future keep the prefetch/data
abort information in different system registers, it's simplest
just to use a completely separate loop from the 32 bit ARM
target, rather than peppering it with ifdefs.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
linux-user/main.c | 82 +++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 82 insertions(+)
diff --git a/linux-user/main.c b/linux-user/main.c
index af82db8..8aba817 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -484,6 +484,9 @@ void cpu_loop(CPUX86State *env)
__r; \
})
+#ifdef TARGET_ABI32
+/* Commpage handling -- there is no commpage for AArch64 */
+
/*
* See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
* Input:
@@ -617,6 +620,7 @@ do_kernel_trap(CPUARMState *env)
return 0;
}
+#endif
static int do_strex(CPUARMState *env)
{
@@ -696,6 +700,7 @@ done:
return segv;
}
+#ifdef TARGET_ABI32
void cpu_loop(CPUARMState *env)
{
CPUState *cs = CPU(arm_env_get_cpu(env));
@@ -908,6 +913,83 @@ void cpu_loop(CPUARMState *env)
}
}
+#else
+
+/* AArch64 main loop */
+void cpu_loop(CPUARMState *env)
+{
+ CPUState *cs = CPU(arm_env_get_cpu(env));
+ int trapnr, sig;
+ target_siginfo_t info;
+ uint32_t addr;
+
+ for (;;) {
+ cpu_exec_start(cs);
+ trapnr = cpu_arm_exec(env);
+ cpu_exec_end(cs);
+
+ switch (trapnr) {
+ case EXCP_SWI:
+ env->xregs[0] = do_syscall(env,
+ env->xregs[8],
+ env->xregs[0],
+ env->xregs[1],
+ env->xregs[2],
+ env->xregs[3],
+ env->xregs[4],
+ env->xregs[5],
+ 0, 0);
+ break;
+ case EXCP_INTERRUPT:
+ /* just indicate that signals should be handled asap */
+ break;
+ case EXCP_UDEF:
+ info.si_signo = SIGILL;
+ info.si_errno = 0;
+ info.si_code = TARGET_ILL_ILLOPN;
+ info._sifields._sigfault._addr = env->pc;
+ queue_signal(env, info.si_signo, &info);
+ break;
+ case EXCP_PREFETCH_ABORT:
+ addr = env->cp15.c6_insn;
+ goto do_segv;
+ case EXCP_DATA_ABORT:
+ addr = env->cp15.c6_data;
+ do_segv:
+ info.si_signo = SIGSEGV;
+ info.si_errno = 0;
+ /* XXX: check env->error_code */
+ info.si_code = TARGET_SEGV_MAPERR;
+ info._sifields._sigfault._addr = addr;
+ queue_signal(env, info.si_signo, &info);
+ break;
+ case EXCP_DEBUG:
+ case EXCP_BKPT:
+ sig = gdb_handlesig(env, TARGET_SIGTRAP);
+ if (sig) {
+ info.si_signo = sig;
+ info.si_errno = 0;
+ info.si_code = TARGET_TRAP_BRKPT;
+ queue_signal(env, info.si_signo, &info);
+ }
+ break;
+ case EXCP_STREX:
+ if (do_strex(env)) {
+ addr = env->cp15.c6_data;
+ goto do_segv;
+ }
+ break;
+ default:
+ fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
+ trapnr);
+ cpu_dump_state(cs, stderr, fprintf, 0);
+ abort();
+ }
+ process_pending_signals(env);
+ }
+}
+#endif /* ndef TARGET_ABI32 */
+
#endif
#ifdef TARGET_UNICORE32
--
1.7.9.5
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH v5 11/21] linux-user: Add syscall number definitions for AArch64
2013-07-01 17:34 [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset Peter Maydell
` (9 preceding siblings ...)
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 10/21] linux-user: Add cpu loop for AArch64 Peter Maydell
@ 2013-07-01 17:35 ` Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 12/21] linux-user: Fix up AArch64 syscall handlers Peter Maydell
` (11 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Peter Maydell @ 2013-07-01 17:35 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Schwab, Alexander Graf, Mian M. Hamayun, patches
From: Alexander Graf <agraf@suse.de>
The AArch64 syscall definitions are all publicly available in the Linux
kernel. Let's add them to our linux-user emulation target, so that we
can easily handle AArch64 syscalls.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Message-id: 1368505980-17151-8-git-send-email-john.rigby@linaro.org
[PMM: changes relating to cpu_loop() removed as they are superseded
by an earlier patch]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
linux-user/aarch64/syscall_nr.h | 323 +++++++++++++++++++++++++++++++++++++++
1 file changed, 323 insertions(+)
create mode 100644 linux-user/aarch64/syscall_nr.h
diff --git a/linux-user/aarch64/syscall_nr.h b/linux-user/aarch64/syscall_nr.h
new file mode 100644
index 0000000..743255d
--- /dev/null
+++ b/linux-user/aarch64/syscall_nr.h
@@ -0,0 +1,323 @@
+/*
+ * This file contains the system call numbers.
+ */
+
+#define TARGET_NR_io_setup 0
+#define TARGET_NR_io_destroy 1
+#define TARGET_NR_io_submit 2
+#define TARGET_NR_io_cancel 3
+#define TARGET_NR_io_getevents 4
+#define TARGET_NR_setxattr 5
+#define TARGET_NR_lsetxattr 6
+#define TARGET_NR_fsetxattr 7
+#define TARGET_NR_getxattr 8
+#define TARGET_NR_lgetxattr 9
+#define TARGET_NR_fgetxattr 10
+#define TARGET_NR_listxattr 11
+#define TARGET_NR_llistxattr 12
+#define TARGET_NR_flistxattr 13
+#define TARGET_NR_removexattr 14
+#define TARGET_NR_lremovexattr 15
+#define TARGET_NR_fremovexattr 16
+#define TARGET_NR_getcwd 17
+#define TARGET_NR_lookup_dcookie 18
+#define TARGET_NR_eventfd2 19
+#define TARGET_NR_epoll_create1 20
+#define TARGET_NR_epoll_ctl 21
+#define TARGET_NR_epoll_pwait 22
+#define TARGET_NR_dup 23
+#define TARGET_NR_dup3 24
+#define TARGET_NR_fcntl 25
+#define TARGET_NR_inotify_init1 26
+#define TARGET_NR_inotify_add_watch 27
+#define TARGET_NR_inotify_rm_watch 28
+#define TARGET_NR_ioctl 29
+#define TARGET_NR_ioprio_set 30
+#define TARGET_NR_ioprio_get 31
+#define TARGET_NR_flock 32
+#define TARGET_NR_mknodat 33
+#define TARGET_NR_mkdirat 34
+#define TARGET_NR_unlinkat 35
+#define TARGET_NR_symlinkat 36
+#define TARGET_NR_linkat 37
+#define TARGET_NR_renameat 38
+#define TARGET_NR_umount2 39
+#define TARGET_NR_mount 40
+#define TARGET_NR_pivot_root 41
+#define TARGET_NR_nfsservctl 42
+#define TARGET_NR_statfs 43
+#define TARGET_NR_fstatfs 44
+#define TARGET_NR_truncate 45
+#define TARGET_NR_ftruncate 46
+#define TARGET_NR_fallocate 47
+#define TARGET_NR_faccessat 48
+#define TARGET_NR_chdir 49
+#define TARGET_NR_fchdir 50
+#define TARGET_NR_chroot 51
+#define TARGET_NR_fchmod 52
+#define TARGET_NR_fchmodat 53
+#define TARGET_NR_fchownat 54
+#define TARGET_NR_fchown 55
+#define TARGET_NR_openat 56
+#define TARGET_NR_close 57
+#define TARGET_NR_vhangup 58
+#define TARGET_NR_pipe2 59
+#define TARGET_NR_quotactl 60
+#define TARGET_NR_getdents64 61
+#define TARGET_NR_lseek 62
+#define TARGET_NR_read 63
+#define TARGET_NR_write 64
+#define TARGET_NR_readv 65
+#define TARGET_NR_writev 66
+#define TARGET_NR_pread64 67
+#define TARGET_NR_pwrite64 68
+#define TARGET_NR_preadv 69
+#define TARGET_NR_pwritev 70
+#define TARGET_NR_sendfile 71
+#define TARGET_NR_pselect6 72
+#define TARGET_NR_ppoll 73
+#define TARGET_NR_signalfd4 74
+#define TARGET_NR_vmsplice 75
+#define TARGET_NR_splice 76
+#define TARGET_NR_tee 77
+#define TARGET_NR_readlinkat 78
+#define TARGET_NR_fstatat64 79
+#define TARGET_NR_fstat 80
+#define TARGET_NR_sync 81
+#define TARGET_NR_fsync 82
+#define TARGET_NR_fdatasync 83
+#define TARGET_NR_sync_file_range2 84
+/* #define TARGET_NR_sync_file_range 84 */
+#define TARGET_NR_timerfd_create 85
+#define TARGET_NR_timerfd_settime 86
+#define TARGET_NR_timerfd_gettime 87
+#define TARGET_NR_utimensat 88
+#define TARGET_NR_acct 89
+#define TARGET_NR_capget 90
+#define TARGET_NR_capset 91
+#define TARGET_NR_personality 92
+#define TARGET_NR_exit 93
+#define TARGET_NR_exit_group 94
+#define TARGET_NR_waitid 95
+#define TARGET_NR_set_tid_address 96
+#define TARGET_NR_unshare 97
+#define TARGET_NR_futex 98
+#define TARGET_NR_set_robust_list 99
+#define TARGET_NR_get_robust_list 100
+#define TARGET_NR_nanosleep 101
+#define TARGET_NR_getitimer 102
+#define TARGET_NR_setitimer 103
+#define TARGET_NR_kexec_load 104
+#define TARGET_NR_init_module 105
+#define TARGET_NR_delete_module 106
+#define TARGET_NR_timer_create 107
+#define TARGET_NR_timer_gettime 108
+#define TARGET_NR_timer_getoverrun 109
+#define TARGET_NR_timer_settime 110
+#define TARGET_NR_timer_delete 111
+#define TARGET_NR_clock_settime 112
+#define TARGET_NR_clock_gettime 113
+#define TARGET_NR_clock_getres 114
+#define TARGET_NR_clock_nanosleep 115
+#define TARGET_NR_syslog 116
+#define TARGET_NR_ptrace 117
+#define TARGET_NR_sched_setparam 118
+#define TARGET_NR_sched_setscheduler 119
+#define TARGET_NR_sched_getscheduler 120
+#define TARGET_NR_sched_getparam 121
+#define TARGET_NR_sched_setaffinity 122
+#define TARGET_NR_sched_getaffinity 123
+#define TARGET_NR_sched_yield 124
+#define TARGET_NR_sched_get_priority_max 125
+#define TARGET_NR_sched_get_priority_min 126
+#define TARGET_NR_sched_rr_get_interval 127
+#define TARGET_NR_restart_syscall 128
+#define TARGET_NR_kill 129
+#define TARGET_NR_tkill 130
+#define TARGET_NR_tgkill 131
+#define TARGET_NR_sigaltstack 132
+#define TARGET_NR_rt_sigsuspend 133
+#define TARGET_NR_rt_sigaction 134
+#define TARGET_NR_rt_sigprocmask 135
+#define TARGET_NR_rt_sigpending 136
+#define TARGET_NR_rt_sigtimedwait 137
+#define TARGET_NR_rt_sigqueueinfo 138
+#define TARGET_NR_rt_sigreturn 139
+#define TARGET_NR_setpriority 140
+#define TARGET_NR_getpriority 141
+#define TARGET_NR_reboot 142
+#define TARGET_NR_setregid 143
+#define TARGET_NR_setgid 144
+#define TARGET_NR_setreuid 145
+#define TARGET_NR_setuid 146
+#define TARGET_NR_setresuid 147
+#define TARGET_NR_getresuid 148
+#define TARGET_NR_setresgid 149
+#define TARGET_NR_getresgid 150
+#define TARGET_NR_setfsuid 151
+#define TARGET_NR_setfsgid 152
+#define TARGET_NR_times 153
+#define TARGET_NR_setpgid 154
+#define TARGET_NR_getpgid 155
+#define TARGET_NR_getsid 156
+#define TARGET_NR_setsid 157
+#define TARGET_NR_getgroups 158
+#define TARGET_NR_setgroups 159
+#define TARGET_NR_uname 160
+#define TARGET_NR_sethostname 161
+#define TARGET_NR_setdomainname 162
+#define TARGET_NR_getrlimit 163
+#define TARGET_NR_setrlimit 164
+#define TARGET_NR_getrusage 165
+#define TARGET_NR_umask 166
+#define TARGET_NR_prctl 167
+#define TARGET_NR_getcpu 168
+#define TARGET_NR_gettimeofday 169
+#define TARGET_NR_settimeofday 170
+#define TARGET_NR_adjtimex 171
+#define TARGET_NR_getpid 172
+#define TARGET_NR_getppid 173
+#define TARGET_NR_getuid 174
+#define TARGET_NR_geteuid 175
+#define TARGET_NR_getgid 176
+#define TARGET_NR_getegid 177
+#define TARGET_NR_gettid 178
+#define TARGET_NR_sysinfo 179
+#define TARGET_NR_mq_open 180
+#define TARGET_NR_mq_unlink 181
+#define TARGET_NR_mq_timedsend 182
+#define TARGET_NR_mq_timedreceive 183
+#define TARGET_NR_mq_notify 184
+#define TARGET_NR_mq_getsetattr 185
+#define TARGET_NR_msgget 186
+#define TARGET_NR_msgctl 187
+#define TARGET_NR_msgrcv 188
+#define TARGET_NR_msgsnd 189
+#define TARGET_NR_semget 190
+#define TARGET_NR_semctl 191
+#define TARGET_NR_semtimedop 192
+#define TARGET_NR_semop 193
+#define TARGET_NR_shmget 194
+#define TARGET_NR_shmctl 195
+#define TARGET_NR_shmat 196
+#define TARGET_NR_shmdt 197
+#define TARGET_NR_socket 198
+#define TARGET_NR_socketpair 199
+#define TARGET_NR_bind 200
+#define TARGET_NR_listen 201
+#define TARGET_NR_accept 202
+#define TARGET_NR_connect 203
+#define TARGET_NR_getsockname 204
+#define TARGET_NR_getpeername 205
+#define TARGET_NR_sendto 206
+#define TARGET_NR_recvfrom 207
+#define TARGET_NR_setsockopt 208
+#define TARGET_NR_getsockopt 209
+#define TARGET_NR_shutdown 210
+#define TARGET_NR_sendmsg 211
+#define TARGET_NR_recvmsg 212
+#define TARGET_NR_readahead 213
+#define TARGET_NR_brk 214
+#define TARGET_NR_munmap 215
+#define TARGET_NR_mremap 216
+#define TARGET_NR_add_key 217
+#define TARGET_NR_request_key 218
+#define TARGET_NR_keyctl 219
+#define TARGET_NR_clone 220
+#define TARGET_NR_execve 221
+#define TARGET_NR_mmap 222
+#define TARGET_NR_fadvise64 223
+#define TARGET_NR_swapon 224
+#define TARGET_NR_swapoff 225
+#define TARGET_NR_mprotect 226
+#define TARGET_NR_msync 227
+#define TARGET_NR_mlock 228
+#define TARGET_NR_munlock 229
+#define TARGET_NR_mlockall 230
+#define TARGET_NR_munlockall 231
+#define TARGET_NR_mincore 232
+#define TARGET_NR_madvise 233
+#define TARGET_NR_remap_file_pages 234
+#define TARGET_NR_mbind 235
+#define TARGET_NR_get_mempolicy 236
+#define TARGET_NR_set_mempolicy 237
+#define TARGET_NR_migrate_pages 238
+#define TARGET_NR_move_pages 239
+#define TARGET_NR_rt_tgsigqueueinfo 240
+#define TARGET_NR_perf_event_open 241
+#define TARGET_NR_accept4 242
+#define TARGET_NR_recvmmsg 243
+#define TARGET_NR_arch_specific_syscall 244
+#define TARGET_NR_wait4 260
+#define TARGET_NR_prlimit64 261
+#define TARGET_NR_fanotify_init 262
+#define TARGET_NR_fanotify_mark 263
+#define TARGET_NR_name_to_handle_at 264
+#define TARGET_NR_open_by_handle_at 265
+#define TARGET_NR_clock_adjtime 266
+#define TARGET_NR_syncfs 267
+#define TARGET_NR_setns 268
+#define TARGET_NR_sendmmsg 269
+#define TARGET_NR_process_vm_readv 270
+#define TARGET_NR_process_vm_writev 271
+#define TARGET_NR_kcmp 272
+#define TARGET_NR_finit_module 273
+#define TARGET_NR_open 1024
+#define TARGET_NR_link 1025
+#define TARGET_NR_unlink 1026
+#define TARGET_NR_mknod 1027
+#define TARGET_NR_chmod 1028
+#define TARGET_NR_chown 1029
+#define TARGET_NR_mkdir 1030
+#define TARGET_NR_rmdir 1031
+#define TARGET_NR_lchown 1032
+#define TARGET_NR_access 1033
+#define TARGET_NR_rename 1034
+#define TARGET_NR_readlink 1035
+#define TARGET_NR_symlink 1036
+#define TARGET_NR_utimes 1037
+#define TARGET_NR_stat 1038
+#define TARGET_NR_lstat 1039
+#define TARGET_NR_pipe 1040
+#define TARGET_NR_dup2 1041
+#define TARGET_NR_epoll_create 1042
+#define TARGET_NR_inotify_init 1043
+#define TARGET_NR_eventfd 1044
+#define TARGET_NR_signalfd 1045
+#define TARGET_NR_sendfile64 1046
+#define TARGET_NR_ftruncate64 1047
+#define TARGET_NR_truncate64 1048
+#define TARGET_NR_stat64 1049
+#define TARGET_NR_lstat64 1050
+#define TARGET_NR_fstat64 1051
+#define TARGET_NR_fcntl64 1052
+/* #define TARGET_NR_fadvise64 1053 */
+#define TARGET_NR_newfstatat 1054
+#define TARGET_NR_fstatfs64 1055
+#define TARGET_NR_statfs64 1056
+#define TARGET_NR_lseek64 1057
+#define TARGET_NR_mmap64 1058
+#define TARGET_NR_alarm 1059
+#define TARGET_NR_getpgrp 1060
+#define TARGET_NR_pause 1061
+#define TARGET_NR_time 1062
+#define TARGET_NR_utime 1063
+#define TARGET_NR_creat 1064
+#define TARGET_NR_getdents 1065
+#define TARGET_NR_futimesat 1066
+#define TARGET_NR_select 1067
+#define TARGET_NR_poll 1068
+#define TARGET_NR_epoll_wait 1069
+#define TARGET_NR_ustat 1070
+#define TARGET_NR_vfork 1071
+#define TARGET_NR_oldwait4 1072
+#define TARGET_NR_recv 1073
+#define TARGET_NR_send 1074
+#define TARGET_NR_bdflush 1075
+#define TARGET_NR_umount 1076
+#define TARGET_NR_uselib 1077
+#define TARGET_NR__sysctl 1078
+#define TARGET_NR_fork 1079
+#define TARGET_NR_syscalls (__NR_fork+1)
+
+#define TARGET_NR_sigreturn 1999
--
1.7.9.5
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH v5 12/21] linux-user: Fix up AArch64 syscall handlers
2013-07-01 17:34 [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset Peter Maydell
` (10 preceding siblings ...)
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 11/21] linux-user: Add syscall number definitions " Peter Maydell
@ 2013-07-01 17:35 ` Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 13/21] linux-user: Add signal handling for AArch64 Peter Maydell
` (10 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Peter Maydell @ 2013-07-01 17:35 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Schwab, Alexander Graf, Mian M. Hamayun, patches
From: Alexander Graf <agraf@suse.de>
Some syscall handlers have special code for ARM enabled that we don't
need on AArch64. Exclude AArch64 in those cases. In other places we
can share struct definitions with other targets or have to provide our
own.
With this patch applied, most syscall definitions in linux-user should
be sound for AArch64.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Message-id: 1368505980-17151-9-git-send-email-john.rigby@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
linux-user/syscall.c | 5 +++--
linux-user/syscall_defs.h | 28 ++++++++++++++++++++++++++--
2 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index cdd0c28..802ec95 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -4695,7 +4695,7 @@ static inline abi_long host_to_target_stat64(void *cpu_env,
abi_ulong target_addr,
struct stat *host_st)
{
-#ifdef TARGET_ARM
+#if defined(TARGET_ARM) && defined(TARGET_ABI32)
if (((CPUARMState *)cpu_env)->eabi) {
struct target_eabi_stat64 *target_st;
@@ -6327,7 +6327,8 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
#endif
#ifdef TARGET_NR_mmap
case TARGET_NR_mmap:
-#if (defined(TARGET_I386) && defined(TARGET_ABI32)) || defined(TARGET_ARM) || \
+#if (defined(TARGET_I386) && defined(TARGET_ABI32)) || \
+ (defined(TARGET_ARM) && defined(TARGET_ABI32)) || \
defined(TARGET_M68K) || defined(TARGET_CRIS) || defined(TARGET_MICROBLAZE) \
|| defined(TARGET_S390X)
{
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index 92c01a9..08f7559 100644
--- a/linux-user/syscall_defs.h
+++ b/linux-user/syscall_defs.h
@@ -1137,7 +1137,8 @@ struct target_winsize {
#define TARGET_MAP_UNINITIALIZED 0x4000000 /* for anonymous mmap, memory could be uninitialized */
#endif
-#if (defined(TARGET_I386) && defined(TARGET_ABI32)) || defined(TARGET_ARM) \
+#if (defined(TARGET_I386) && defined(TARGET_ABI32)) \
+ || (defined(TARGET_ARM) && defined(TARGET_ABI32)) \
|| defined(TARGET_CRIS) || defined(TARGET_UNICORE32) \
|| defined(TARGET_OPENRISC)
struct target_stat {
@@ -1836,6 +1837,28 @@ struct target_stat {
abi_long st_blocks;
abi_ulong __unused[3];
};
+#elif defined(TARGET_AARCH64)
+struct target_stat {
+ abi_ulong st_dev;
+ abi_ulong st_ino;
+ unsigned int st_mode;
+ unsigned int st_nlink;
+ unsigned int st_uid;
+ unsigned int st_gid;
+ abi_ulong st_rdev;
+ abi_ulong _pad1;
+ abi_long st_size;
+ int st_blksize;
+ int __pad2;
+ abi_long st_blocks;
+ abi_long target_st_atime;
+ abi_ulong target_st_atime_nsec;
+ abi_long target_st_mtime;
+ abi_ulong target_st_mtime_nsec;
+ abi_long target_st_ctime;
+ abi_ulong target_st_ctime_nsec;
+ unsigned int __unused[2];
+};
#elif defined(TARGET_OPENRISC)
struct target_stat {
abi_ulong st_dev;
@@ -1918,7 +1941,8 @@ struct target_statfs64 {
uint32_t f_spare[6];
};
#elif (defined(TARGET_PPC64) || defined(TARGET_X86_64) || \
- defined(TARGET_SPARC64)) && !defined(TARGET_ABI32)
+ defined(TARGET_SPARC64) || defined(TARGET_AARCH64)) && \
+ !defined(TARGET_ABI32)
struct target_statfs {
abi_long f_type;
abi_long f_bsize;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH v5 13/21] linux-user: Add signal handling for AArch64
2013-07-01 17:34 [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset Peter Maydell
` (11 preceding siblings ...)
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 12/21] linux-user: Fix up AArch64 syscall handlers Peter Maydell
@ 2013-07-01 17:35 ` Peter Maydell
2013-09-02 12:44 ` Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 14/21] linux-user: Make sure NWFPE code is 32 bit ARM only Peter Maydell
` (9 subsequent siblings)
22 siblings, 1 reply; 29+ messages in thread
From: Peter Maydell @ 2013-07-01 17:35 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Schwab, Alexander Graf, Mian M. Hamayun, patches
From: Andreas Schwab <schwab@suse.de>
This patch adds signal handling for AArch64. The code is based on the
respective source in the Linux kernel.
Signed-off-by: Andreas Schwab <schwab@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Message-id: 1368505980-17151-10-git-send-email-john.rigby@linaro.org
[PMM: fixed style nits: tabs, long lines;
pulled target_signal.h in from a later patch; it fits better here]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
linux-user/aarch64/target_signal.h | 29 ++++
linux-user/signal.c | 254 ++++++++++++++++++++++++++++++++++++
2 files changed, 283 insertions(+)
create mode 100644 linux-user/aarch64/target_signal.h
diff --git a/linux-user/aarch64/target_signal.h b/linux-user/aarch64/target_signal.h
new file mode 100644
index 0000000..d69a2d2
--- /dev/null
+++ b/linux-user/aarch64/target_signal.h
@@ -0,0 +1,29 @@
+#ifndef TARGET_SIGNAL_H
+#define TARGET_SIGNAL_H
+
+#include "cpu.h"
+
+/* this struct defines a stack used during syscall handling */
+
+typedef struct target_sigaltstack {
+ abi_ulong ss_sp;
+ abi_long ss_flags;
+ abi_ulong ss_size;
+} target_stack_t;
+
+
+/*
+ * sigaltstack controls
+ */
+#define TARGET_SS_ONSTACK 1
+#define TARGET_SS_DISABLE 2
+
+#define TARGET_MINSIGSTKSZ 2048
+#define TARGET_SIGSTKSZ 8192
+
+static inline abi_ulong get_sp_from_cpustate(CPUARMState *state)
+{
+ return state->xregs[31];
+}
+
+#endif /* TARGET_SIGNAL_H */
diff --git a/linux-user/signal.c b/linux-user/signal.c
index c4e20dc..076a9a2 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -1090,6 +1090,260 @@ badframe:
return 0;
}
+#elif defined(TARGET_AARCH64)
+
+struct target_sigcontext {
+ uint64_t fault_address;
+ /* AArch64 registers */
+ uint64_t regs[31];
+ uint64_t sp;
+ uint64_t pc;
+ uint64_t pstate;
+ /* 4K reserved for FP/SIMD state and future expansion */
+ char __reserved[4096] __attribute__((__aligned__(16)));
+};
+
+struct target_ucontext {
+ abi_ulong tuc_flags;
+ abi_ulong tuc_link;
+ target_stack_t tuc_stack;
+ target_sigset_t tuc_sigmask;
+ /* glibc uses a 1024-bit sigset_t */
+ char __unused[1024 / 8 - sizeof(target_sigset_t)];
+ /* last for future expansion */
+ struct target_sigcontext tuc_mcontext;
+};
+
+/*
+ * Header to be used at the beginning of structures extending the user
+ * context. Such structures must be placed after the rt_sigframe on the stack
+ * and be 16-byte aligned. The last structure must be a dummy one with the
+ * magic and size set to 0.
+ */
+struct target_aarch64_ctx {
+ uint32_t magic;
+ uint32_t size;
+};
+
+#define TARGET_FPSIMD_MAGIC 0x46508001
+
+struct target_fpsimd_context {
+ struct target_aarch64_ctx head;
+ uint32_t fpsr;
+ uint32_t fpcr;
+ uint64_t vregs[32 * 2];
+};
+
+/*
+ * Auxiliary context saved in the sigcontext.__reserved array. Not exported to
+ * user space as it will change with the addition of new context. User space
+ * should check the magic/size information.
+ */
+struct target_aux_context {
+ struct target_fpsimd_context fpsimd;
+ /* additional context to be added before "end" */
+ struct target_aarch64_ctx end;
+};
+
+struct target_rt_sigframe {
+ struct target_siginfo info;
+ struct target_ucontext uc;
+ uint64_t fp;
+ uint64_t lr;
+ uint32_t tramp[2];
+};
+
+static int target_setup_sigframe(struct target_rt_sigframe *sf,
+ CPUARMState *env, target_sigset_t *set)
+{
+ int i;
+ struct target_aux_context *aux =
+ (struct target_aux_context *)sf->uc.tuc_mcontext.__reserved;
+
+ /* set up the stack frame for unwinding */
+ __put_user(env->xregs[29], &sf->fp);
+ __put_user(env->xregs[30], &sf->lr);
+
+ for (i = 0; i < 31; i++) {
+ __put_user(env->xregs[i], &sf->uc.tuc_mcontext.regs[i]);
+ }
+ __put_user(env->xregs[31], &sf->uc.tuc_mcontext.sp);
+ __put_user(env->pc, &sf->uc.tuc_mcontext.pc);
+ __put_user(env->pstate, &sf->uc.tuc_mcontext.pstate);
+
+ __put_user(/*current->thread.fault_address*/ 0,
+ &sf->uc.tuc_mcontext.fault_address);
+
+ for (i = 0; i < TARGET_NSIG_WORDS; i++) {
+ __put_user(set->sig[i], &sf->uc.tuc_sigmask.sig[i]);
+ }
+
+ for (i = 0; i < 32 * 2; i++) {
+ __put_user(env->vfp.regs[i], &aux->fpsimd.vregs[i]);
+ }
+ __put_user(/*env->fpsr*/0, &aux->fpsimd.fpsr);
+ __put_user(/*env->fpcr*/0, &aux->fpsimd.fpcr);
+ __put_user(TARGET_FPSIMD_MAGIC, &aux->fpsimd.head.magic);
+ __put_user(sizeof(struct target_fpsimd_context),
+ &aux->fpsimd.head.size);
+
+ /* set the "end" magic */
+ __put_user(0, &aux->end.magic);
+ __put_user(0, &aux->end.size);
+
+ return 0;
+}
+
+static int target_restore_sigframe(CPUARMState *env,
+ struct target_rt_sigframe *sf)
+{
+ sigset_t set;
+ int i;
+ struct target_aux_context *aux =
+ (struct target_aux_context *)sf->uc.tuc_mcontext.__reserved;
+ uint32_t magic, size;
+
+ target_to_host_sigset(&set, &sf->uc.tuc_sigmask);
+ sigprocmask(SIG_SETMASK, &set, NULL);
+
+ for (i = 0; i < 31; i++) {
+ __get_user(env->xregs[i], &sf->uc.tuc_mcontext.regs[i]);
+ }
+
+ __get_user(env->xregs[31], &sf->uc.tuc_mcontext.sp);
+ __get_user(env->pc, &sf->uc.tuc_mcontext.pc);
+ __get_user(env->pstate, &sf->uc.tuc_mcontext.pstate);
+
+ __get_user(magic, &aux->fpsimd.head.magic);
+ __get_user(size, &aux->fpsimd.head.size);
+
+ if (magic != TARGET_FPSIMD_MAGIC
+ || size != sizeof(struct target_fpsimd_context)) {
+ return 1;
+ }
+
+ for (i = 0; i < 32 * 2; i++) {
+ __get_user(env->vfp.regs[i], &aux->fpsimd.vregs[i]);
+ }
+
+ return 0;
+}
+
+static abi_ulong get_sigframe(struct target_sigaction *ka, CPUARMState *env)
+{
+ abi_ulong sp;
+
+ sp = env->xregs[31];
+
+ /*
+ * This is the X/Open sanctioned signal stack switching.
+ */
+ if ((ka->sa_flags & SA_ONSTACK) && !sas_ss_flags(sp)) {
+ sp = target_sigaltstack_used.ss_sp + target_sigaltstack_used.ss_size;
+ }
+
+ sp = (sp - sizeof(struct target_rt_sigframe)) & ~15;
+
+ return sp;
+}
+
+static void target_setup_frame(int usig, struct target_sigaction *ka,
+ target_siginfo_t *info, target_sigset_t *set,
+ CPUARMState *env)
+{
+ struct target_rt_sigframe *frame;
+ abi_ulong frame_addr;
+
+ frame_addr = get_sigframe(ka, env);
+ if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0)) {
+ goto give_sigsegv;
+ }
+
+ __put_user(0, &frame->uc.tuc_flags);
+ __put_user(0, &frame->uc.tuc_link);
+
+ __put_user(target_sigaltstack_used.ss_sp,
+ &frame->uc.tuc_stack.ss_sp);
+ __put_user(sas_ss_flags(env->xregs[31]),
+ &frame->uc.tuc_stack.ss_flags);
+ __put_user(target_sigaltstack_used.ss_size,
+ &frame->uc.tuc_stack.ss_size);
+ target_setup_sigframe(frame, env, set);
+ /* mov x8,#__NR_rt_sigreturn; svc #0 */
+ __put_user(0xd2801168, &frame->tramp[0]);
+ __put_user(0xd4000001, &frame->tramp[1]);
+ env->xregs[0] = usig;
+ env->xregs[31] = frame_addr;
+ env->xregs[29] = env->xregs[31] + offsetof(struct target_rt_sigframe, fp);
+ env->pc = ka->_sa_handler;
+ env->xregs[30] = env->xregs[31] +
+ offsetof(struct target_rt_sigframe, tramp);
+ if (info) {
+ if (copy_siginfo_to_user(&frame->info, info)) {
+ goto give_sigsegv;
+ }
+ env->xregs[1] = frame_addr + offsetof(struct target_rt_sigframe, info);
+ env->xregs[2] = frame_addr + offsetof(struct target_rt_sigframe, uc);
+ }
+
+ unlock_user_struct(frame, frame_addr, 1);
+ return;
+
+ give_sigsegv:
+ unlock_user_struct(frame, frame_addr, 1);
+ force_sig(TARGET_SIGSEGV);
+}
+
+static void setup_rt_frame(int sig, struct target_sigaction *ka,
+ target_siginfo_t *info, target_sigset_t *set,
+ CPUARMState *env)
+{
+ target_setup_frame(sig, ka, info, set, env);
+}
+
+static void setup_frame(int sig, struct target_sigaction *ka,
+ target_sigset_t *set, CPUARMState *env)
+{
+ target_setup_frame(sig, ka, 0, set, env);
+}
+
+long do_rt_sigreturn(CPUARMState *env)
+{
+ struct target_rt_sigframe *frame;
+ abi_ulong frame_addr = env->xregs[31];
+
+ if (frame_addr & 15) {
+ goto badframe;
+ }
+
+ if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1)) {
+ goto badframe;
+ }
+
+ if (target_restore_sigframe(env, frame)) {
+ goto badframe;
+ }
+
+ if (do_sigaltstack(frame_addr +
+ offsetof(struct target_rt_sigframe, uc.tuc_stack),
+ 0, get_sp_from_cpustate(env)) == -EFAULT) {
+ goto badframe;
+ }
+
+ unlock_user_struct(frame, frame_addr, 0);
+ return env->xregs[0];
+
+ badframe:
+ unlock_user_struct(frame, frame_addr, 0);
+ force_sig(TARGET_SIGSEGV);
+ return 0;
+}
+
+long do_sigreturn(CPUARMState *env)
+{
+ return do_rt_sigreturn(env);
+}
+
#elif defined(TARGET_ARM)
struct target_sigcontext {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH v5 14/21] linux-user: Make sure NWFPE code is 32 bit ARM only
2013-07-01 17:34 [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset Peter Maydell
` (12 preceding siblings ...)
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 13/21] linux-user: Add signal handling for AArch64 Peter Maydell
@ 2013-07-01 17:35 ` Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 15/21] target-arm: Implement cpu_set_tls() and cpu_clone_regs() for AArch64 Peter Maydell
` (8 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Peter Maydell @ 2013-07-01 17:35 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Schwab, Alexander Graf, Mian M. Hamayun, patches
On ARM, linux-user emulation includes NWFPE support for emulating the
ancient FPA floating point coprocessor. This has long since been
superseded by VFP and is only required for legacy binaries. The
AArch64 linux-user target doesn't compile in NWFPE support, so make
sure the relevant code is protected by suitable ifdefs.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
linux-user/qemu.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/linux-user/qemu.h b/linux-user/qemu.h
index b10e957..d51d827 100644
--- a/linux-user/qemu.h
+++ b/linux-user/qemu.h
@@ -79,7 +79,7 @@ struct vm86_saved_state {
};
#endif
-#ifdef TARGET_ARM
+#if defined(TARGET_ARM) && defined(TARGET_ABI32)
/* FPU emulator */
#include "nwfpe/fpa11.h"
#endif
@@ -103,8 +103,10 @@ struct emulated_sigtable {
typedef struct TaskState {
pid_t ts_tid; /* tid (or pid) of this task */
#ifdef TARGET_ARM
+# ifdef TARGET_ABI32
/* FPA state */
FPA11 fpa;
+# endif
int swi_errno;
#endif
#ifdef TARGET_UNICORE32
--
1.7.9.5
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH v5 15/21] target-arm: Implement cpu_set_tls() and cpu_clone_regs() for AArch64
2013-07-01 17:34 [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset Peter Maydell
` (13 preceding siblings ...)
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 14/21] linux-user: Make sure NWFPE code is 32 bit ARM only Peter Maydell
@ 2013-07-01 17:35 ` Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 16/21] linux-user: Add AArch64 termbits.h definitions Peter Maydell
` (7 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Peter Maydell @ 2013-07-01 17:35 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Schwab, Alexander Graf, Mian M. Hamayun, patches
From: Alexander Graf <agraf@suse.de>
[PMM: pulled out from another patch because this is going to need to
morph into a patch putting them into linux-user/aarch64/target_cpu.h
as soon as my patch doing that move for existing CPUs lands; also
use #ifdefs rather than is_a64().]
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu.h | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 78614a4..f9288d1 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -303,10 +303,17 @@ int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
int mmu_idx);
#define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
+#ifndef TARGET_AARCH64
static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
{
env->cp15.c13_tls2 = newtls;
}
+#else
+static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
+{
+ env->sr.tpidr_el0 = newtls;
+}
+#endif
#define CPSR_M (0x1f)
#define CPSR_T (1 << 5)
@@ -795,12 +802,22 @@ static inline int cpu_mmu_index (CPUARMState *env)
}
#if defined(CONFIG_USER_ONLY)
+#ifndef TARGET_AARCH64
static inline void cpu_clone_regs(CPUARMState *env, target_ulong newsp)
{
if (newsp)
env->regs[13] = newsp;
env->regs[0] = 0;
}
+#else
+static inline void cpu_clone_regs(CPUARMState *env, target_ulong newsp)
+{
+ if (newsp) {
+ env->xregs[31] = newsp;
+ }
+ env->xregs[0] = 0;
+}
+#endif
#endif
#include "exec/cpu-all.h"
--
1.7.9.5
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH v5 16/21] linux-user: Add AArch64 termbits.h definitions
2013-07-01 17:34 [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset Peter Maydell
` (14 preceding siblings ...)
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 15/21] target-arm: Implement cpu_set_tls() and cpu_clone_regs() for AArch64 Peter Maydell
@ 2013-07-01 17:35 ` Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 17/21] linux-user: Add AArch64 support Peter Maydell
` (6 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Peter Maydell @ 2013-07-01 17:35 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Schwab, Alexander Graf, Mian M. Hamayun, patches
From: Alexander Graf <agraf@suse.de>
Add the AArch64 termbits.h with all the target's termios related
constants and structures.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: John Rigby <john.rigby@linaro.org>
[PMM: split out from another patch]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
linux-user/aarch64/termbits.h | 220 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 220 insertions(+)
create mode 100644 linux-user/aarch64/termbits.h
diff --git a/linux-user/aarch64/termbits.h b/linux-user/aarch64/termbits.h
new file mode 100644
index 0000000..b64ba97
--- /dev/null
+++ b/linux-user/aarch64/termbits.h
@@ -0,0 +1,220 @@
+/* from asm/termbits.h */
+/* NOTE: exactly the same as i386 */
+
+#define TARGET_NCCS 19
+
+struct target_termios {
+ unsigned int c_iflag; /* input mode flags */
+ unsigned int c_oflag; /* output mode flags */
+ unsigned int c_cflag; /* control mode flags */
+ unsigned int c_lflag; /* local mode flags */
+ unsigned char c_line; /* line discipline */
+ unsigned char c_cc[TARGET_NCCS]; /* control characters */
+};
+
+/* c_iflag bits */
+#define TARGET_IGNBRK 0000001
+#define TARGET_BRKINT 0000002
+#define TARGET_IGNPAR 0000004
+#define TARGET_PARMRK 0000010
+#define TARGET_INPCK 0000020
+#define TARGET_ISTRIP 0000040
+#define TARGET_INLCR 0000100
+#define TARGET_IGNCR 0000200
+#define TARGET_ICRNL 0000400
+#define TARGET_IUCLC 0001000
+#define TARGET_IXON 0002000
+#define TARGET_IXANY 0004000
+#define TARGET_IXOFF 0010000
+#define TARGET_IMAXBEL 0020000
+#define TARGET_IUTF8 0040000
+
+/* c_oflag bits */
+#define TARGET_OPOST 0000001
+#define TARGET_OLCUC 0000002
+#define TARGET_ONLCR 0000004
+#define TARGET_OCRNL 0000010
+#define TARGET_ONOCR 0000020
+#define TARGET_ONLRET 0000040
+#define TARGET_OFILL 0000100
+#define TARGET_OFDEL 0000200
+#define TARGET_NLDLY 0000400
+#define TARGET_NL0 0000000
+#define TARGET_NL1 0000400
+#define TARGET_CRDLY 0003000
+#define TARGET_CR0 0000000
+#define TARGET_CR1 0001000
+#define TARGET_CR2 0002000
+#define TARGET_CR3 0003000
+#define TARGET_TABDLY 0014000
+#define TARGET_TAB0 0000000
+#define TARGET_TAB1 0004000
+#define TARGET_TAB2 0010000
+#define TARGET_TAB3 0014000
+#define TARGET_XTABS 0014000
+#define TARGET_BSDLY 0020000
+#define TARGET_BS0 0000000
+#define TARGET_BS1 0020000
+#define TARGET_VTDLY 0040000
+#define TARGET_VT0 0000000
+#define TARGET_VT1 0040000
+#define TARGET_FFDLY 0100000
+#define TARGET_FF0 0000000
+#define TARGET_FF1 0100000
+
+/* c_cflag bit meaning */
+#define TARGET_CBAUD 0010017
+#define TARGET_B0 0000000 /* hang up */
+#define TARGET_B50 0000001
+#define TARGET_B75 0000002
+#define TARGET_B110 0000003
+#define TARGET_B134 0000004
+#define TARGET_B150 0000005
+#define TARGET_B200 0000006
+#define TARGET_B300 0000007
+#define TARGET_B600 0000010
+#define TARGET_B1200 0000011
+#define TARGET_B1800 0000012
+#define TARGET_B2400 0000013
+#define TARGET_B4800 0000014
+#define TARGET_B9600 0000015
+#define TARGET_B19200 0000016
+#define TARGET_B38400 0000017
+#define TARGET_EXTA B19200
+#define TARGET_EXTB B38400
+#define TARGET_CSIZE 0000060
+#define TARGET_CS5 0000000
+#define TARGET_CS6 0000020
+#define TARGET_CS7 0000040
+#define TARGET_CS8 0000060
+#define TARGET_CSTOPB 0000100
+#define TARGET_CREAD 0000200
+#define TARGET_PARENB 0000400
+#define TARGET_PARODD 0001000
+#define TARGET_HUPCL 0002000
+#define TARGET_CLOCAL 0004000
+#define TARGET_CBAUDEX 0010000
+#define TARGET_B57600 0010001
+#define TARGET_B115200 0010002
+#define TARGET_B230400 0010003
+#define TARGET_B460800 0010004
+#define TARGET_CIBAUD 002003600000 /* input baud rate (not used) */
+#define TARGET_CMSPAR 010000000000 /* mark or space (stick) parity */
+#define TARGET_CRTSCTS 020000000000 /* flow control */
+
+/* c_lflag bits */
+#define TARGET_ISIG 0000001
+#define TARGET_ICANON 0000002
+#define TARGET_XCASE 0000004
+#define TARGET_ECHO 0000010
+#define TARGET_ECHOE 0000020
+#define TARGET_ECHOK 0000040
+#define TARGET_ECHONL 0000100
+#define TARGET_NOFLSH 0000200
+#define TARGET_TOSTOP 0000400
+#define TARGET_ECHOCTL 0001000
+#define TARGET_ECHOPRT 0002000
+#define TARGET_ECHOKE 0004000
+#define TARGET_FLUSHO 0010000
+#define TARGET_PENDIN 0040000
+#define TARGET_IEXTEN 0100000
+
+/* c_cc character offsets */
+#define TARGET_VINTR 0
+#define TARGET_VQUIT 1
+#define TARGET_VERASE 2
+#define TARGET_VKILL 3
+#define TARGET_VEOF 4
+#define TARGET_VTIME 5
+#define TARGET_VMIN 6
+#define TARGET_VSWTC 7
+#define TARGET_VSTART 8
+#define TARGET_VSTOP 9
+#define TARGET_VSUSP 10
+#define TARGET_VEOL 11
+#define TARGET_VREPRINT 12
+#define TARGET_VDISCARD 13
+#define TARGET_VWERASE 14
+#define TARGET_VLNEXT 15
+#define TARGET_VEOL2 16
+
+/* ioctls */
+
+#define TARGET_TCGETS 0x5401
+#define TARGET_TCSETS 0x5402
+#define TARGET_TCSETSW 0x5403
+#define TARGET_TCSETSF 0x5404
+#define TARGET_TCGETA 0x5405
+#define TARGET_TCSETA 0x5406
+#define TARGET_TCSETAW 0x5407
+#define TARGET_TCSETAF 0x5408
+#define TARGET_TCSBRK 0x5409
+#define TARGET_TCXONC 0x540A
+#define TARGET_TCFLSH 0x540B
+
+#define TARGET_TIOCEXCL 0x540C
+#define TARGET_TIOCNXCL 0x540D
+#define TARGET_TIOCSCTTY 0x540E
+#define TARGET_TIOCGPGRP 0x540F
+#define TARGET_TIOCSPGRP 0x5410
+#define TARGET_TIOCOUTQ 0x5411
+#define TARGET_TIOCSTI 0x5412
+#define TARGET_TIOCGWINSZ 0x5413
+#define TARGET_TIOCSWINSZ 0x5414
+#define TARGET_TIOCMGET 0x5415
+#define TARGET_TIOCMBIS 0x5416
+#define TARGET_TIOCMBIC 0x5417
+#define TARGET_TIOCMSET 0x5418
+#define TARGET_TIOCGSOFTCAR 0x5419
+#define TARGET_TIOCSSOFTCAR 0x541A
+#define TARGET_FIONREAD 0x541B
+#define TARGET_TIOCINQ TARGET_FIONREAD
+#define TARGET_TIOCLINUX 0x541C
+#define TARGET_TIOCCONS 0x541D
+#define TARGET_TIOCGSERIAL 0x541E
+#define TARGET_TIOCSSERIAL 0x541F
+#define TARGET_TIOCPKT 0x5420
+#define TARGET_FIONBIO 0x5421
+#define TARGET_TIOCNOTTY 0x5422
+#define TARGET_TIOCSETD 0x5423
+#define TARGET_TIOCGETD 0x5424
+#define TARGET_TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */
+#define TARGET_TIOCTTYGSTRUCT 0x5426 /* For debugging only */
+#define TARGET_TIOCSBRK 0x5427 /* BSD compatibility */
+#define TARGET_TIOCCBRK 0x5428 /* BSD compatibility */
+#define TARGET_TIOCGSID 0x5429 /* Return the session ID of FD */
+#define TARGET_TIOCGPTN TARGET_IOR('T', 0x30, unsigned int)
+ /* Get Pty Number (of pty-mux device) */
+#define TARGET_TIOCSPTLCK TARGET_IOW('T', 0x31, int)
+ /* Lock/unlock Pty */
+
+#define TARGET_FIONCLEX 0x5450 /* these numbers need to be adjusted. */
+#define TARGET_FIOCLEX 0x5451
+#define TARGET_FIOASYNC 0x5452
+#define TARGET_TIOCSERCONFIG 0x5453
+#define TARGET_TIOCSERGWILD 0x5454
+#define TARGET_TIOCSERSWILD 0x5455
+#define TARGET_TIOCGLCKTRMIOS 0x5456
+#define TARGET_TIOCSLCKTRMIOS 0x5457
+#define TARGET_TIOCSERGSTRUCT 0x5458 /* For debugging only */
+#define TARGET_TIOCSERGETLSR 0x5459 /* Get line status register */
+#define TARGET_TIOCSERGETMULTI 0x545A /* Get multiport config */
+#define TARGET_TIOCSERSETMULTI 0x545B /* Set multiport config */
+
+#define TARGET_TIOCMIWAIT 0x545C
+ /* wait for a change on serial input line(s) */
+#define TARGET_TIOCGICOUNT 0x545D
+ /* read serial port inline interrupt counts */
+#define TARGET_TIOCGHAYESESP 0x545E /* Get Hayes ESP configuration */
+#define TARGET_TIOCSHAYESESP 0x545F /* Set Hayes ESP configuration */
+
+/* Used for packet mode */
+#define TARGET_TIOCPKT_DATA 0
+#define TARGET_TIOCPKT_FLUSHREAD 1
+#define TARGET_TIOCPKT_FLUSHWRITE 2
+#define TARGET_TIOCPKT_STOP 4
+#define TARGET_TIOCPKT_START 8
+#define TARGET_TIOCPKT_NOSTOP 16
+#define TARGET_TIOCPKT_DOSTOP 32
+
+#define TARGET_TIOCSER_TEMT 0x01 /* Transmitter physically empty */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH v5 17/21] linux-user: Add AArch64 support
2013-07-01 17:34 [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset Peter Maydell
` (15 preceding siblings ...)
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 16/21] linux-user: Add AArch64 termbits.h definitions Peter Maydell
@ 2013-07-01 17:35 ` Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 18/21] linux-user: AArch64 requires at least 3.8.0 Peter Maydell
` (5 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Peter Maydell @ 2013-07-01 17:35 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Schwab, Alexander Graf, Mian M. Hamayun, patches
From: Alexander Graf <agraf@suse.de>
This patch adds support for AArch64 in all the small corners of
linux-user and beyond.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Message-id: 1368505980-17151-11-git-send-email-john.rigby@linaro.org
[PMM:
* removed some unnecessary #defines from syscall.h
* catch attempts to use a 32 bit only cpu with aarch64-linux-user
* termios stuff moved into its own patch
]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
linux-user/aarch64/syscall.h | 8 ++++++++
linux-user/elfload.c | 15 +++++++++++++--
linux-user/main.c | 16 ++++++++++++++++
3 files changed, 37 insertions(+), 2 deletions(-)
create mode 100644 linux-user/aarch64/syscall.h
diff --git a/linux-user/aarch64/syscall.h b/linux-user/aarch64/syscall.h
new file mode 100644
index 0000000..e863640
--- /dev/null
+++ b/linux-user/aarch64/syscall.h
@@ -0,0 +1,8 @@
+struct target_pt_regs {
+ uint64_t regs[31];
+ uint64_t sp;
+ uint64_t pc;
+ uint64_t pstate;
+};
+
+#define UNAME_MACHINE "aarch64"
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index ddef23e..9d8631d 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -267,16 +267,26 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUX86State *en
#define ELF_START_MMAP 0x80000000
-#define elf_check_arch(x) ( (x) == EM_ARM )
+#define elf_check_arch(x) ((x) == ELF_MACHINE)
+#define ELF_ARCH ELF_MACHINE
+
+#ifdef TARGET_AARCH64
+#define ELF_CLASS ELFCLASS64
+#else
#define ELF_CLASS ELFCLASS32
-#define ELF_ARCH EM_ARM
+#endif
static inline void init_thread(struct target_pt_regs *regs,
struct image_info *infop)
{
abi_long stack = infop->start_stack;
memset(regs, 0, sizeof(*regs));
+
+#ifdef TARGET_AARCH64
+ regs->pc = infop->entry & ~0x3ULL;
+ regs->sp = stack;
+#else
regs->ARM_cpsr = 0x10;
if (infop->entry & 1)
regs->ARM_cpsr |= CPSR_T;
@@ -290,6 +300,7 @@ static inline void init_thread(struct target_pt_regs *regs,
/* For uClinux PIC binaries. */
/* XXX: Linux does this only on ARM with no MMU (do we care ?) */
regs->ARM_r10 = infop->start_data;
+#endif
}
#define ELF_NREG 18
diff --git a/linux-user/main.c b/linux-user/main.c
index 8aba817..e76e987 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -3965,6 +3965,22 @@ int main(int argc, char **argv, char **envp)
cpu_x86_load_seg(env, R_FS, 0);
cpu_x86_load_seg(env, R_GS, 0);
#endif
+#elif defined(TARGET_AARCH64)
+ {
+ int i;
+
+ if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
+ fprintf(stderr,
+ "The selected ARM CPU does not support 64 bit mode\n");
+ exit(1);
+ }
+
+ for (i = 0; i < 31; i++) {
+ env->xregs[i] = regs->regs[i];
+ }
+ env->pc = regs->pc;
+ env->xregs[31] = regs->sp;
+ }
#elif defined(TARGET_ARM)
{
int i;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH v5 18/21] linux-user: AArch64 requires at least 3.8.0
2013-07-01 17:34 [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset Peter Maydell
` (16 preceding siblings ...)
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 17/21] linux-user: Add AArch64 support Peter Maydell
@ 2013-07-01 17:35 ` Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 19/21] configure: Add handling code for AArch64 targets Peter Maydell
` (4 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Peter Maydell @ 2013-07-01 17:35 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Schwab, Alexander Graf, Mian M. Hamayun, patches
From: Alexander Graf <agraf@suse.de>
Glibc 1.17 checks for the host kernel version on startup. Unfortunately,
it also checks whether the host kernel version is recent enough for the
target to run at all.
Since AArch64 support only got introduced in 3.8.0, that means that glibc
refuses to run on any older kernel version than that.
To allow for execution of linux-user guests even on older host kernels,
let's always fake the kernel version to 3.8.0 on AArch64 guests.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Message-id: 1368505980-17151-13-git-send-email-john.rigby@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
linux-user/syscall.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 802ec95..c2497e4 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -304,7 +304,12 @@ static int sys_uname(struct new_utsname *buf)
memset(buf, 0, sizeof(*buf));
COPY_UTSNAME_FIELD(buf->sysname, uts_buf.sysname);
COPY_UTSNAME_FIELD(buf->nodename, uts_buf.nodename);
+#ifdef TARGET_AARCH64
+ /* glibc refuses to run on older kernels */
+ COPY_UTSNAME_FIELD(buf->release, "3.8.0");
+#else
COPY_UTSNAME_FIELD(buf->release, uts_buf.release);
+#endif
COPY_UTSNAME_FIELD(buf->version, uts_buf.version);
COPY_UTSNAME_FIELD(buf->machine, uts_buf.machine);
#ifdef _GNU_SOURCE
--
1.7.9.5
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH v5 19/21] configure: Add handling code for AArch64 targets
2013-07-01 17:34 [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset Peter Maydell
` (17 preceding siblings ...)
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 18/21] linux-user: AArch64 requires at least 3.8.0 Peter Maydell
@ 2013-07-01 17:35 ` Peter Maydell
2013-09-02 16:44 ` Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 20/21] default-configs: Add config for aarch64-linux-user Peter Maydell
` (3 subsequent siblings)
22 siblings, 1 reply; 29+ messages in thread
From: Peter Maydell @ 2013-07-01 17:35 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Schwab, Alexander Graf, Mian M. Hamayun, patches
From: Alexander Graf <agraf@suse.de>
Add the necessary code to configure to handle AArch64 as a target
CPU (we already have some code for supporting it as host). Note
that this doesn't enable the AArch64 targets yet.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Message-id: 1368505980-17151-12-git-send-email-john.rigby@linaro.org
[PMM:
* don't need to set TARGET_ABI_DIR to aarch64 as that is the default
* don't build nwfpe -- this is 32 bit legacy only
* rewrite commit message
* add aarch64 to the list of "fdt required" targets
]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
configure | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/configure b/configure
index 0e0adde..2f83771 100755
--- a/configure
+++ b/configure
@@ -2491,7 +2491,7 @@ fi
fdt_required=no
for target in $target_list; do
case $target in
- arm*-softmmu|ppc*-softmmu|microblaze*-softmmu)
+ aarch64*-softmmu|arm*-softmmu|ppc*-softmmu|microblaze*-softmmu)
fdt_required=yes
;;
esac
@@ -4169,6 +4169,13 @@ case "$target_name" in
target_nptl="yes"
gdb_xml_files="arm-core.xml arm-vfp.xml arm-vfp3.xml arm-neon.xml"
;;
+ aarch64)
+ TARGET_BASE_ARCH=arm
+ bflt="yes"
+ target_nptl="yes"
+ gdb_xml_files="aarch64-core.xml aarch64-fpu.xml"
+ target_long_alignment=8
+ ;;
cris)
target_nptl="yes"
;;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH v5 20/21] default-configs: Add config for aarch64-linux-user
2013-07-01 17:34 [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset Peter Maydell
` (18 preceding siblings ...)
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 19/21] configure: Add handling code for AArch64 targets Peter Maydell
@ 2013-07-01 17:35 ` Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 21/21] default-configs: Add config for aarch64-softmmu Peter Maydell
` (2 subsequent siblings)
22 siblings, 0 replies; 29+ messages in thread
From: Peter Maydell @ 2013-07-01 17:35 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Schwab, Alexander Graf, Mian M. Hamayun, patches
Add a config for aarch64-linux-user, thereby enabling it as
a valid target.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
default-configs/aarch64-linux-user.mak | 3 +++
1 file changed, 3 insertions(+)
create mode 100644 default-configs/aarch64-linux-user.mak
diff --git a/default-configs/aarch64-linux-user.mak b/default-configs/aarch64-linux-user.mak
new file mode 100644
index 0000000..3df7de5
--- /dev/null
+++ b/default-configs/aarch64-linux-user.mak
@@ -0,0 +1,3 @@
+# Default configuration for aarch64-linux-user
+
+CONFIG_GDBSTUB_XML=y
--
1.7.9.5
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Qemu-devel] [PATCH v5 21/21] default-configs: Add config for aarch64-softmmu
2013-07-01 17:34 [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset Peter Maydell
` (19 preceding siblings ...)
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 20/21] default-configs: Add config for aarch64-linux-user Peter Maydell
@ 2013-07-01 17:35 ` Peter Maydell
2013-07-01 19:07 ` [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset Peter Maydell
2013-09-03 10:05 ` Andreas Färber
22 siblings, 0 replies; 29+ messages in thread
From: Peter Maydell @ 2013-07-01 17:35 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Schwab, Alexander Graf, Mian M. Hamayun, patches
Add a config for aarch64-softmmu; this enables building of this target.
The resulting executable doesn't know about any 64 bit CPUs, but all
the 32 bit CPUs and board models work.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
default-configs/aarch64-softmmu.mak | 82 +++++++++++++++++++++++++++++++++++
1 file changed, 82 insertions(+)
create mode 100644 default-configs/aarch64-softmmu.mak
diff --git a/default-configs/aarch64-softmmu.mak b/default-configs/aarch64-softmmu.mak
new file mode 100644
index 0000000..27cbe3d
--- /dev/null
+++ b/default-configs/aarch64-softmmu.mak
@@ -0,0 +1,82 @@
+# Default configuration for arm-softmmu
+
+include pci.mak
+include usb.mak
+CONFIG_GDBSTUB_XML=y
+CONFIG_VGA=y
+CONFIG_ISA_MMIO=y
+CONFIG_NAND=y
+CONFIG_ECC=y
+CONFIG_SERIAL=y
+CONFIG_PTIMER=y
+CONFIG_SD=y
+CONFIG_MAX7310=y
+CONFIG_WM8750=y
+CONFIG_TWL92230=y
+CONFIG_TSC2005=y
+CONFIG_LM832X=y
+CONFIG_TMP105=y
+CONFIG_STELLARIS=y
+CONFIG_STELLARIS_INPUT=y
+CONFIG_STELLARIS_ENET=y
+CONFIG_SSD0303=y
+CONFIG_SSD0323=y
+CONFIG_ADS7846=y
+CONFIG_MAX111X=y
+CONFIG_SSI=y
+CONFIG_SSI_SD=y
+CONFIG_SSI_M25P80=y
+CONFIG_LAN9118=y
+CONFIG_SMC91C111=y
+CONFIG_DS1338=y
+CONFIG_PFLASH_CFI01=y
+CONFIG_PFLASH_CFI02=y
+CONFIG_MICRODRIVE=y
+CONFIG_USB_MUSB=y
+
+CONFIG_ARM9MPCORE=y
+CONFIG_ARM11MPCORE=y
+CONFIG_ARM15MPCORE=y
+
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_KVM=$(CONFIG_KVM)
+CONFIG_ARM_TIMER=y
+CONFIG_ARM_MPTIMER=y
+CONFIG_PL011=y
+CONFIG_PL022=y
+CONFIG_PL031=y
+CONFIG_PL041=y
+CONFIG_PL050=y
+CONFIG_PL061=y
+CONFIG_PL080=y
+CONFIG_PL110=y
+CONFIG_PL181=y
+CONFIG_PL190=y
+CONFIG_PL310=y
+CONFIG_PL330=y
+CONFIG_CADENCE=y
+CONFIG_XGMAC=y
+CONFIG_EXYNOS4=y
+CONFIG_PXA2XX=y
+CONFIG_BITBANG_I2C=y
+CONFIG_FRAMEBUFFER=y
+CONFIG_XILINX_SPIPS=y
+
+CONFIG_A9SCU=y
+CONFIG_MARVELL_88W8618=y
+CONFIG_OMAP=y
+CONFIG_TSC210X=y
+CONFIG_BLIZZARD=y
+CONFIG_ONENAND=y
+CONFIG_TUSB6010=y
+CONFIG_IMX=y
+CONFIG_MAINSTONE=y
+CONFIG_NSERIES=y
+CONFIG_REALVIEW=y
+CONFIG_ZAURUS=y
+CONFIG_ZYNQ=y
+
+CONFIG_VERSATILE_PCI=y
+CONFIG_VERSATILE_I2C=y
+
+CONFIG_SDHCI=y
--
1.7.9.5
^ permalink raw reply related [flat|nested] 29+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset
2013-07-01 17:34 [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset Peter Maydell
` (20 preceding siblings ...)
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 21/21] default-configs: Add config for aarch64-softmmu Peter Maydell
@ 2013-07-01 19:07 ` Peter Maydell
2013-07-18 13:31 ` Peter Maydell
2013-09-03 10:05 ` Andreas Färber
22 siblings, 1 reply; 29+ messages in thread
From: Peter Maydell @ 2013-07-01 19:07 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Schwab, Alexander Graf, Mian M. Hamayun, patches
On 1 July 2013 18:34, Peter Maydell <peter.maydell@linaro.org> wrote:
> This patchset is v5 of the "preparation patchset" that started
> off with Alex, was passed to John Rigby and now to me.
Also available via git:
git://git.linaro.org/people/pmaydell/qemu-arm.git aarch64
(caution: branch likely to rebase in future)
-- PMM
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset
2013-07-01 19:07 ` [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset Peter Maydell
@ 2013-07-18 13:31 ` Peter Maydell
2013-08-05 13:13 ` Peter Maydell
0 siblings, 1 reply; 29+ messages in thread
From: Peter Maydell @ 2013-07-18 13:31 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Schwab, Alexander Graf, Mian M. Hamayun, patches
On 1 July 2013 20:07, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 1 July 2013 18:34, Peter Maydell <peter.maydell@linaro.org> wrote:
>> This patchset is v5 of the "preparation patchset" that started
>> off with Alex, was passed to John Rigby and now to me.
>
> Also available via git:
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git aarch64
> (caution: branch likely to rebase in future)
I'm not going to bother reposting the whole patchset since
the changes are trivial, but for the benefit of people basing
other patchsets on top of this, I've rebased it on current
master and updated the git branch above.
-- PMM
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset
2013-07-18 13:31 ` Peter Maydell
@ 2013-08-05 13:13 ` Peter Maydell
0 siblings, 0 replies; 29+ messages in thread
From: Peter Maydell @ 2013-08-05 13:13 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Schwab, Alexander Graf, Mian M. Hamayun, patches
On 18 July 2013 14:31, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 1 July 2013 20:07, Peter Maydell <peter.maydell@linaro.org> wrote:
>> On 1 July 2013 18:34, Peter Maydell <peter.maydell@linaro.org> wrote:
>>> This patchset is v5 of the "preparation patchset" that started
>>> off with Alex, was passed to John Rigby and now to me.
>>
>> Also available via git:
>>
>> git://git.linaro.org/people/pmaydell/qemu-arm.git aarch64
>> (caution: branch likely to rebase in future)
>
> I'm not going to bother reposting the whole patchset since
> the changes are trivial, but for the benefit of people basing
> other patchsets on top of this, I've rebased it on current
> master and updated the git branch above.
Git branch updated again on current master.
-- PMM
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [Qemu-devel] [PATCH v5 13/21] linux-user: Add signal handling for AArch64
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 13/21] linux-user: Add signal handling for AArch64 Peter Maydell
@ 2013-09-02 12:44 ` Peter Maydell
0 siblings, 0 replies; 29+ messages in thread
From: Peter Maydell @ 2013-09-02 12:44 UTC (permalink / raw)
To: QEMU Developers
Cc: Andreas Schwab, Alexander Graf, Mian M. Hamayun, Patch Tracking
On 1 July 2013 18:35, Peter Maydell <peter.maydell@linaro.org> wrote:
> From: Andreas Schwab <schwab@suse.de>
>
> This patch adds signal handling for AArch64. The code is based on the
> respective source in the Linux kernel.
Couple of minor things I noticed, and will fix for an upcoming v6:
> +typedef struct target_sigaltstack {
> + abi_ulong ss_sp;
> + abi_long ss_flags;
The kernel defines this field as 'int', not 'long', so so should we
(would only cause a problem on a big endian host I think,
given the struct layout means ss_size ends up at the same
offset either way.)
> + abi_ulong ss_size;
> +} target_stack_t;
> + for (i = 0; i < 32 * 2; i++) {
> + __put_user(env->vfp.regs[i], &aux->fpsimd.vregs[i]);
> + }
This is wrong for the (currently hypothetical) case of bigendian
(the other __put_user() are fine because that macro does an
endianness swap if needed, but this is actually an array of
32 int128_t.
-- PMM
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [Qemu-devel] [PATCH v5 19/21] configure: Add handling code for AArch64 targets
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 19/21] configure: Add handling code for AArch64 targets Peter Maydell
@ 2013-09-02 16:44 ` Peter Maydell
2013-09-02 17:03 ` Peter Maydell
0 siblings, 1 reply; 29+ messages in thread
From: Peter Maydell @ 2013-09-02 16:44 UTC (permalink / raw)
To: QEMU Developers
Cc: Andreas Schwab, Alexander Graf, Mian M. Hamayun, Patch Tracking
On 1 July 2013 18:35, Peter Maydell <peter.maydell@linaro.org> wrote:
> From: Alexander Graf <agraf@suse.de>
>
> Add the necessary code to configure to handle AArch64 as a target
> CPU (we already have some code for supporting it as host). Note
> that this doesn't enable the AArch64 targets yet.
> + aarch64)
> + TARGET_BASE_ARCH=arm
> + bflt="yes"
> + target_nptl="yes"
> + gdb_xml_files="aarch64-core.xml aarch64-fpu.xml"
> + target_long_alignment=8
This is a holdover from before Paolo cleaned up the ABI
type alignment handling -- we need to add handling in
abitypes.h now.
-- PMM
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [Qemu-devel] [PATCH v5 19/21] configure: Add handling code for AArch64 targets
2013-09-02 16:44 ` Peter Maydell
@ 2013-09-02 17:03 ` Peter Maydell
0 siblings, 0 replies; 29+ messages in thread
From: Peter Maydell @ 2013-09-02 17:03 UTC (permalink / raw)
To: QEMU Developers
Cc: Andreas Schwab, Laurent Vivier, Alexander Graf, Mian M. Hamayun,
Patch Tracking
On 2 September 2013 17:44, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 1 July 2013 18:35, Peter Maydell <peter.maydell@linaro.org> wrote:
>> From: Alexander Graf <agraf@suse.de>
>>
>> Add the necessary code to configure to handle AArch64 as a target
>> CPU (we already have some code for supporting it as host). Note
>> that this doesn't enable the AArch64 targets yet.
>> + aarch64)
>> + TARGET_BASE_ARCH=arm
>> + bflt="yes"
>> + target_nptl="yes"
>> + gdb_xml_files="aarch64-core.xml aarch64-fpu.xml"
>> + target_long_alignment=8
>
> This is a holdover from before Paolo cleaned up the ABI
> type alignment handling -- we need to add handling in
> abitypes.h now.
Except that the default abitypes.h code is correct for
AArch64, so no extra code required. I'll just drop that
line (and the equally out of date target_nptl="yes").
Aside: I wonder why we have
#ifdef TARGET_ARM
#define ABI_LLONG_ALIGNMENT 4
#endif
given that the ARM procedure calling standard says that
64 bit integers are 8 aligned, and gcc's __alignof__
agrees with that (gcc (Ubuntu/Linaro 4.7.2-2ubuntu1) 4.7.2)
Laurent's commit message from 2011 for
c2e3dee6e gives gcc output for ARM of "alignof(long long) 4"
so either that wasn't APCS or gcc was buggy...
-- PMM
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset
2013-07-01 17:34 [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset Peter Maydell
` (21 preceding siblings ...)
2013-07-01 19:07 ` [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset Peter Maydell
@ 2013-09-03 10:05 ` Andreas Färber
22 siblings, 0 replies; 29+ messages in thread
From: Andreas Färber @ 2013-09-03 10:05 UTC (permalink / raw)
To: Peter Maydell
Cc: Andreas Schwab, patches, qemu-devel, Mian M. Hamayun,
Alexander Graf
Am 01.07.2013 19:34, schrieb Peter Maydell:
> I've left the 'global cpu_env variable' patch alone since
> there wasn't any consensus about what the best approach was;
> it's a pretty minor (and textually localized) thing anyway so
> easy to fix in future if it becomes an actual problem.
Ack.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 29+ messages in thread
end of thread, other threads:[~2013-09-03 10:05 UTC | newest]
Thread overview: 29+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2013-07-01 17:34 [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 01/21] target-arm: Abstract out load/store from a vaddr in AArch32 Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 02/21] target-arm: Extract the disas struct to a header file Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 03/21] target-arm: Export cpu_env Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 04/21] target-arm: Fix target_ulong/uint32_t confusions Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 05/21] target-arm: Pass DisasContext* to gen_set_pc_im() Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 06/21] target-arm: Prepare translation for AArch64 code Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 07/21] target-arm: Add AArch64 translation stub Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 08/21] gdbstub: Add AArch64 support Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 09/21] linux-user: Don't treat AArch64 cpu names specially Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 10/21] linux-user: Add cpu loop for AArch64 Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 11/21] linux-user: Add syscall number definitions " Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 12/21] linux-user: Fix up AArch64 syscall handlers Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 13/21] linux-user: Add signal handling for AArch64 Peter Maydell
2013-09-02 12:44 ` Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 14/21] linux-user: Make sure NWFPE code is 32 bit ARM only Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 15/21] target-arm: Implement cpu_set_tls() and cpu_clone_regs() for AArch64 Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 16/21] linux-user: Add AArch64 termbits.h definitions Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 17/21] linux-user: Add AArch64 support Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 18/21] linux-user: AArch64 requires at least 3.8.0 Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 19/21] configure: Add handling code for AArch64 targets Peter Maydell
2013-09-02 16:44 ` Peter Maydell
2013-09-02 17:03 ` Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 20/21] default-configs: Add config for aarch64-linux-user Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 21/21] default-configs: Add config for aarch64-softmmu Peter Maydell
2013-07-01 19:07 ` [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset Peter Maydell
2013-07-18 13:31 ` Peter Maydell
2013-08-05 13:13 ` Peter Maydell
2013-09-03 10:05 ` Andreas Färber
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