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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Cc: Andreas Schwab <schwab@suse.de>, Alexander Graf <agraf@suse.de>,
	"Mian M. Hamayun" <m.hamayun@virtualopensystems.com>,
	patches@linaro.org
Subject: [Qemu-devel] [PATCH v5 02/21] target-arm: Extract the disas struct to a header file
Date: Mon,  1 Jul 2013 18:35:01 +0100	[thread overview]
Message-ID: <1372700120-8896-3-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1372700120-8896-1-git-send-email-peter.maydell@linaro.org>

From: Alexander Graf <agraf@suse.de>

We will need to share the disassembly status struct between AArch32 and
AArch64 modes. So put it into a header file that both sides can use.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Message-id: 1368505980-17151-2-git-send-email-john.rigby@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/translate.c |   24 +-----------------------
 target-arm/translate.h |   27 +++++++++++++++++++++++++++
 2 files changed, 28 insertions(+), 23 deletions(-)
 create mode 100644 target-arm/translate.h

diff --git a/target-arm/translate.c b/target-arm/translate.c
index 1618524..1a9c1a0 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -45,29 +45,7 @@
 
 #define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)
 
-/* internal defines */
-typedef struct DisasContext {
-    target_ulong pc;
-    int is_jmp;
-    /* Nonzero if this instruction has been conditionally skipped.  */
-    int condjmp;
-    /* The label that will be jumped to when the instruction is skipped.  */
-    int condlabel;
-    /* Thumb-2 conditional execution bits.  */
-    int condexec_mask;
-    int condexec_cond;
-    struct TranslationBlock *tb;
-    int singlestep_enabled;
-    int thumb;
-    int bswap_code;
-#if !defined(CONFIG_USER_ONLY)
-    int user;
-#endif
-    int vfp_enabled;
-    int vec_len;
-    int vec_stride;
-} DisasContext;
-
+#include "translate.h"
 static uint32_t gen_opc_condexec_bits[OPC_BUF_SIZE];
 
 #if defined(CONFIG_USER_ONLY)
diff --git a/target-arm/translate.h b/target-arm/translate.h
new file mode 100644
index 0000000..e727bc6
--- /dev/null
+++ b/target-arm/translate.h
@@ -0,0 +1,27 @@
+#ifndef TARGET_ARM_TRANSLATE_H
+#define TARGET_ARM_TRANSLATE_H
+
+/* internal defines */
+typedef struct DisasContext {
+    target_ulong pc;
+    int is_jmp;
+    /* Nonzero if this instruction has been conditionally skipped.  */
+    int condjmp;
+    /* The label that will be jumped to when the instruction is skipped.  */
+    int condlabel;
+    /* Thumb-2 conditional execution bits.  */
+    int condexec_mask;
+    int condexec_cond;
+    struct TranslationBlock *tb;
+    int singlestep_enabled;
+    int thumb;
+    int bswap_code;
+#if !defined(CONFIG_USER_ONLY)
+    int user;
+#endif
+    int vfp_enabled;
+    int vec_len;
+    int vec_stride;
+} DisasContext;
+
+#endif /* TARGET_ARM_TRANSLATE_H */
-- 
1.7.9.5

  parent reply	other threads:[~2013-07-01 18:03 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-07-01 17:34 [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 01/21] target-arm: Abstract out load/store from a vaddr in AArch32 Peter Maydell
2013-07-01 17:35 ` Peter Maydell [this message]
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 03/21] target-arm: Export cpu_env Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 04/21] target-arm: Fix target_ulong/uint32_t confusions Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 05/21] target-arm: Pass DisasContext* to gen_set_pc_im() Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 06/21] target-arm: Prepare translation for AArch64 code Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 07/21] target-arm: Add AArch64 translation stub Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 08/21] gdbstub: Add AArch64 support Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 09/21] linux-user: Don't treat AArch64 cpu names specially Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 10/21] linux-user: Add cpu loop for AArch64 Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 11/21] linux-user: Add syscall number definitions " Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 12/21] linux-user: Fix up AArch64 syscall handlers Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 13/21] linux-user: Add signal handling for AArch64 Peter Maydell
2013-09-02 12:44   ` Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 14/21] linux-user: Make sure NWFPE code is 32 bit ARM only Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 15/21] target-arm: Implement cpu_set_tls() and cpu_clone_regs() for AArch64 Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 16/21] linux-user: Add AArch64 termbits.h definitions Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 17/21] linux-user: Add AArch64 support Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 18/21] linux-user: AArch64 requires at least 3.8.0 Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 19/21] configure: Add handling code for AArch64 targets Peter Maydell
2013-09-02 16:44   ` Peter Maydell
2013-09-02 17:03     ` Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 20/21] default-configs: Add config for aarch64-linux-user Peter Maydell
2013-07-01 17:35 ` [Qemu-devel] [PATCH v5 21/21] default-configs: Add config for aarch64-softmmu Peter Maydell
2013-07-01 19:07 ` [Qemu-devel] [PATCH v5 00/21] AArch64 preparation patchset Peter Maydell
2013-07-18 13:31   ` Peter Maydell
2013-08-05 13:13     ` Peter Maydell
2013-09-03 10:05 ` Andreas Färber

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