[Qemu-devel] [PATCH 0/2] target-alpha prep work for qom cpu changes

[Qemu-devel] [PATCH 0/2] target-alpha prep work for qom cpu changes

[Richard Henderson]

As discussed in the QOM thread.


r~


Richard Henderson (2):
  target-alpha: Copy singlestep_enabled to DisasContext
  target-alpha: Copy implver to DisasContext

 target-alpha/translate.c | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

-- 
1.8.1.4

[Qemu-devel] [PATCH 1/2] target-alpha: Copy singlestep_enabled to DisasContext

[Richard Henderson]

Prepare for removing env from DisasContext.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-alpha/translate.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 4db16db..b59f919 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -46,6 +46,8 @@ struct DisasContext {
     int tb_rm;
     /* Current flush-to-zero setting for this TB.  */
     int tb_ftz;
+
+    bool singlestep_enabled;
 };
 
 /* Return values from translate_one, indicating the state of the TB.
@@ -380,7 +382,7 @@ static int use_goto_tb(DisasContext *ctx, uint64_t dest)
     /* Check for the dest on the same page as the start of the TB.  We
        also want to suppress goto_tb in the case of single-steping and IO.  */
     return (((ctx->tb->pc ^ dest) & TARGET_PAGE_MASK) == 0
-            && !ctx->env->singlestep_enabled
+            && !ctx->singlestep_enabled
             && !(ctx->tb->cflags & CF_LAST_IO));
 }
 
@@ -3396,6 +3398,7 @@ static inline void gen_intermediate_code_internal(CPUAlphaState *env,
     ctx.env = env;
     ctx.pc = pc_start;
     ctx.mem_idx = cpu_mmu_index(env);
+    ctx.singlestep_enabled = env->singlestep_enabled;
 
     /* ??? Every TB begins with unset rounding mode, to be initialized on
        the first fp insn of the TB.  Alternately we could define a proper
@@ -3452,7 +3455,7 @@ static inline void gen_intermediate_code_internal(CPUAlphaState *env,
                 || tcg_ctx.gen_opc_ptr >= gen_opc_end
                 || num_insns >= max_insns
                 || singlestep
-                || env->singlestep_enabled)) {
+                || ctx.singlestep_enabled)) {
             ret = EXIT_PC_STALE;
         }
     } while (ret == NO_EXIT);
@@ -3469,7 +3472,7 @@ static inline void gen_intermediate_code_internal(CPUAlphaState *env,
         tcg_gen_movi_i64(cpu_pc, ctx.pc);
         /* FALLTHRU */
     case EXIT_PC_UPDATED:
-        if (env->singlestep_enabled) {
+        if (ctx.singlestep_enabled) {
             gen_excp_1(EXCP_DEBUG, 0);
         } else {
             tcg_gen_exit_tb(0);
-- 
1.8.1.4

[Qemu-devel] [PATCH 2/2] target-alpha: Copy implver to DisasContext

[Richard Henderson]

Which allows removing env from DisasContext.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-alpha/translate.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index b59f919..7dac0c8 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -38,7 +38,6 @@
 typedef struct DisasContext DisasContext;
 struct DisasContext {
     struct TranslationBlock *tb;
-    CPUAlphaState *env;
     uint64_t pc;
     int mem_idx;
 
@@ -47,6 +46,9 @@ struct DisasContext {
     /* Current flush-to-zero setting for this TB.  */
     int tb_ftz;
 
+    /* implver value for this CPU.  */
+    int implver;
+
     bool singlestep_enabled;
 };
 
@@ -2246,8 +2248,9 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
             break;
         case 0x6C:
             /* IMPLVER */
-            if (rc != 31)
-                tcg_gen_movi_i64(cpu_ir[rc], ctx->env->implver);
+            if (rc != 31) {
+                tcg_gen_movi_i64(cpu_ir[rc], ctx->implver);
+            }
             break;
         default:
             goto invalid_opc;
@@ -3395,9 +3398,9 @@ static inline void gen_intermediate_code_internal(CPUAlphaState *env,
     gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
 
     ctx.tb = tb;
-    ctx.env = env;
     ctx.pc = pc_start;
     ctx.mem_idx = cpu_mmu_index(env);
+    ctx.implver = env->implver;
     ctx.singlestep_enabled = env->singlestep_enabled;
 
     /* ??? Every TB begins with unset rounding mode, to be initialized on
-- 
1.8.1.4

Re: [Qemu-devel] [PATCH 1/2] target-alpha: Copy singlestep_enabled to DisasContext

[Andreas Färber]

Am 01.07.2013 22:19, schrieb Richard Henderson:
> Prepare for removing env from DisasContext.
> 
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
>  target-alpha/translate.c | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/target-alpha/translate.c b/target-alpha/translate.c
> index 4db16db..b59f919 100644
> --- a/target-alpha/translate.c
> +++ b/target-alpha/translate.c
> @@ -46,6 +46,8 @@ struct DisasContext {
>      int tb_rm;
>      /* Current flush-to-zero setting for this TB.  */
>      int tb_ftz;
> +
> +    bool singlestep_enabled;

env->singlestep_enabled is an int containing flags. Below it's only used
as a boolean though, so

Reviewed-by: Andreas Färber <afaerber@suse.de>

Thanks,
Andreas

>  };
>  
>  /* Return values from translate_one, indicating the state of the TB.
> @@ -380,7 +382,7 @@ static int use_goto_tb(DisasContext *ctx, uint64_t dest)
>      /* Check for the dest on the same page as the start of the TB.  We
>         also want to suppress goto_tb in the case of single-steping and IO.  */
>      return (((ctx->tb->pc ^ dest) & TARGET_PAGE_MASK) == 0
> -            && !ctx->env->singlestep_enabled
> +            && !ctx->singlestep_enabled
>              && !(ctx->tb->cflags & CF_LAST_IO));
>  }
>  
> @@ -3396,6 +3398,7 @@ static inline void gen_intermediate_code_internal(CPUAlphaState *env,
>      ctx.env = env;
>      ctx.pc = pc_start;
>      ctx.mem_idx = cpu_mmu_index(env);
> +    ctx.singlestep_enabled = env->singlestep_enabled;
>  
>      /* ??? Every TB begins with unset rounding mode, to be initialized on
>         the first fp insn of the TB.  Alternately we could define a proper
> @@ -3452,7 +3455,7 @@ static inline void gen_intermediate_code_internal(CPUAlphaState *env,
>                  || tcg_ctx.gen_opc_ptr >= gen_opc_end
>                  || num_insns >= max_insns
>                  || singlestep
> -                || env->singlestep_enabled)) {
> +                || ctx.singlestep_enabled)) {
>              ret = EXIT_PC_STALE;
>          }
>      } while (ret == NO_EXIT);
> @@ -3469,7 +3472,7 @@ static inline void gen_intermediate_code_internal(CPUAlphaState *env,
>          tcg_gen_movi_i64(cpu_pc, ctx.pc);
>          /* FALLTHRU */
>      case EXIT_PC_UPDATED:
> -        if (env->singlestep_enabled) {
> +        if (ctx.singlestep_enabled) {
>              gen_excp_1(EXCP_DEBUG, 0);
>          } else {
>              tcg_gen_exit_tb(0);

-- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg

Re: [Qemu-devel] [PATCH 2/2] target-alpha: Copy implver to DisasContext

[Andreas Färber]

Am 01.07.2013 22:19, schrieb Richard Henderson:
> Which allows removing env from DisasContext.
> 
> Signed-off-by: Richard Henderson <rth@twiddle.net>

Reviewed-by: Andreas Färber <afaerber@suse.de>

I notice that implver is only ever assigned in CPUs' instance_init, so a
candidate for moving to AlphaCPUClass as a follow-up.

Andreas

-- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg

Re: [Qemu-devel] [PATCH 0/2] target-alpha prep work for qom cpu changes

[Andreas Färber]

Am 01.07.2013 22:19, schrieb Richard Henderson:
> As discussed in the QOM thread.

Thanks, applying to qom-cpu-next to rebase qom-cpu-11:
https://github.com/afaerber/qemu-cpu/commits/qom-cpu-next

Andreas

> Richard Henderson (2):
>   target-alpha: Copy singlestep_enabled to DisasContext
>   target-alpha: Copy implver to DisasContext
> 
>  target-alpha/translate.c | 20 +++++++++++++-------
>  1 file changed, 13 insertions(+), 7 deletions(-)
> 


-- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg