Re: [Qemu-devel] [Qemu-ppc] [PATCH 16/17] ppc64: Enable QEMU to run on POWER 8 DD1 chip.

[Benjamin Herrenschmidt <benh@kernel.crashing.org>]

On Thu, 2013-07-04 at 07:54 +0200, Andreas Färber wrote:
> Am 27.06.2013 08:45, schrieb Alexey Kardashevskiy:
> > From: Prerna Saxena <prerna@linux.vnet.ibm.com>
> > 
> > This patch enables QEMU to launch VM guests on POWER8 chip. I have tested
> > this to work with BML kernel on P8 dd1 chip.
> > 
> > Signed-off-by: Prerna Saxena <prerna@linux.vnet.ibm.com>
> > Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> > Reviewed-by: Paul Mackerras <paulus@samba.org>
> 
> The subject slightly hides what the patch is actually doing:
> Suggest "target-ppc: Add POWER8 v0.1 CPU model"?

It's 1.0 anyway :-)

> What's DD1, should that be added to the textual description?

"DD" is how we call our chip revisions internally. DD1 is 1.0, DD1.1 is
1.1, etc..

Cheers,
Ben.

> > ---
> >  target-ppc/cpu-models.c     |    3 +++
> >  target-ppc/cpu-models.h     |    1 +
> >  target-ppc/translate_init.c |   34 ++++++++++++++++++++++++++++++++++
> >  3 files changed, 38 insertions(+)
> > 
> > diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c
> > index 9bb68c8..f8c64dd 100644
> > --- a/target-ppc/cpu-models.c
> > +++ b/target-ppc/cpu-models.c
> > @@ -1145,6 +1145,8 @@
> >                  "POWER7 v2.1")
> >      POWERPC_DEF("POWER7_v2.3",   CPU_POWERPC_POWER7_v23,             POWER7,
> >                  "POWER7 v2.3")
> > +    POWERPC_DEF("POWER8_v0.1",   CPU_POWERPC_POWER8_v01,             POWER8,
> > +                "POWER8 v0.1")
> >      POWERPC_DEF("970",           CPU_POWERPC_970,                    970,
> >                  "PowerPC 970")
> >      POWERPC_DEF("970fx_v1.0",    CPU_POWERPC_970FX_v10,              970FX,
> > @@ -1390,6 +1392,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] = {
> >      { "Dino",  "POWER3" },
> >      { "POWER3+", "631" },
> >      { "POWER7", "POWER7_v2.3" },
> > +    { "POWER8", "POWER8_v0.1" },
> >      { "970fx", "970fx_v3.1" },
> >      { "970mp", "970mp_v1.1" },
> >      { "Apache", "RS64" },
> > diff --git a/target-ppc/cpu-models.h b/target-ppc/cpu-models.h
> > index 262ca47..b349ad2 100644
> > --- a/target-ppc/cpu-models.h
> > +++ b/target-ppc/cpu-models.h
> > @@ -556,6 +556,7 @@ enum {
> >      CPU_POWERPC_POWER7_v20         = 0x003F0200,
> >      CPU_POWERPC_POWER7_v21         = 0x003F0201,
> >      CPU_POWERPC_POWER7_v23         = 0x003F0203,
> > +    CPU_POWERPC_POWER8_v01         = 0x004B0100,
> 
> Are you sure this PVR is v0.1 and not v1.0?
> 
> Rest looks okay, although I wouldn't know how to check all flags.
> 
> Andreas
> 
> >      CPU_POWERPC_970                = 0x00390202,
> >      CPU_POWERPC_970FX_v10          = 0x00391100,
> >      CPU_POWERPC_970FX_v20          = 0x003C0200,
> > diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> > index 95aebf7..2502758 100644
> > --- a/target-ppc/translate_init.c
> > +++ b/target-ppc/translate_init.c
> > @@ -7011,6 +7011,40 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
> >      pcc->l1_dcache_size = 0x8000;
> >      pcc->l1_icache_size = 0x8000;
> >  }
> > +
> > +POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
> > +{
> > +    DeviceClass *dc = DEVICE_CLASS(oc);
> > +    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
> > +
> > +    dc->desc = "POWER8";
> > +    pcc->init_proc = init_proc_POWER7;
> > +    pcc->check_pow = check_pow_nocheck;
> > +    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
> > +                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
> > +                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
> > +                       PPC_FLOAT_STFIWX |
> > +                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
> > +                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
> > +                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
> > +                       PPC_64B | PPC_ALTIVEC |
> > +                       PPC_SEGMENT_64B | PPC_SLBI |
> > +                       PPC_POPCNTB | PPC_POPCNTWD;
> > +    pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX;
> > +    pcc->msr_mask = 0x800000000204FF36ULL;
> > +    pcc->mmu_model = POWERPC_MMU_2_06;
> > +#if defined(CONFIG_SOFTMMU)
> > +    pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
> > +#endif
> > +    pcc->excp_model = POWERPC_EXCP_POWER7;
> > +    pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
> > +    pcc->bfd_mach = bfd_mach_ppc64;
> > +    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
> > +                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
> > +                 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR;
> > +    pcc->l1_dcache_size = 0x8000;
> > +    pcc->l1_icache_size = 0x8000;
> > +}
> >  #endif /* defined (TARGET_PPC64) */
> >  
> >  
> 
>