From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50820) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UuqLN-0004ts-Qy for qemu-devel@nongnu.org; Thu, 04 Jul 2013 16:41:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UuqLK-0002NY-ES for qemu-devel@nongnu.org; Thu, 04 Jul 2013 16:41:33 -0400 Received: from mail-pa0-x22b.google.com ([2607:f8b0:400e:c03::22b]:54055) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UuqLK-0002NL-7C for qemu-devel@nongnu.org; Thu, 04 Jul 2013 16:41:30 -0400 Received: by mail-pa0-f43.google.com with SMTP id hz11so1588308pad.30 for ; Thu, 04 Jul 2013 13:41:29 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Thu, 4 Jul 2013 13:40:58 -0700 Message-Id: <1372970462-10338-12-git-send-email-rth@twiddle.net> In-Reply-To: <1372970462-10338-1-git-send-email-rth@twiddle.net> References: <1372970462-10338-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v4 11/15] tcg-arm: Use AT_PLATFORM to detect the host ISA List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, aliguori@us.ibm.com With this we can generate armv7 insns even when the OS compiles for a lower common denominator. The macros are arranged so that when we do compile for a given ISA, all of the runtime checks for that ISA are optimized away. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index fde1715..4710046 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -41,6 +41,8 @@ # endif #endif +static int arm_arch = __ARM_ARCH; + #if defined(__ARM_ARCH_5T__) \ || defined(__ARM_ARCH_5TE__) || defined(__ARM_ARCH_5TEJ__) # define use_armv5t_instructions 1 @@ -48,8 +50,8 @@ # define use_armv5t_instructions use_armv6_instructions #endif -#define use_armv6_instructions (__ARM_ARCH >= 6) -#define use_armv7_instructions (__ARM_ARCH >= 7) +#define use_armv6_instructions (__ARM_ARCH >= 6 || arm_arch >= 6) +#define use_armv7_instructions (__ARM_ARCH >= 7 || arm_arch >= 7) #ifndef use_idiv_instructions bool use_idiv_instructions; @@ -2028,12 +2030,22 @@ static const TCGTargetOpDef arm_op_defs[] = { static void tcg_target_init(TCGContext *s) { -#if defined(CONFIG_GETAUXVAL) && !defined(use_idiv_instructions) +#if defined(CONFIG_GETAUXVAL) + /* Only probe for the platform and capabilities if we havn't already + determined maximum values at compile time. */ +# if !defined(use_idiv_instructions) { unsigned long hwcap = getauxval(AT_HWCAP); use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0; } -#endif +# endif + if (__ARM_ARCH < 7) { + const char *pl = (const char *)getauxval(AT_PLATFORM); + if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') { + arm_arch = pl[1] - '0'; + } + } +#endif /* GETAUXVAL */ tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff); tcg_regset_set32(tcg_target_call_clobber_regs, 0, -- 1.8.1.4