From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44852) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UwPrf-0001Xr-Mh for qemu-devel@nongnu.org; Tue, 09 Jul 2013 00:49:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UwPra-00077O-VU for qemu-devel@nongnu.org; Tue, 09 Jul 2013 00:49:23 -0400 Message-ID: <1373345328.4446.115.camel@pasglop> From: Benjamin Herrenschmidt Date: Tue, 09 Jul 2013 14:48:48 +1000 In-Reply-To: <51DB8639.9050906@ozlabs.ru> References: <1372315560-5478-1-git-send-email-aik@ozlabs.ru> <1372315560-5478-3-git-send-email-aik@ozlabs.ru> <87fvvo29ps.fsf@codemonkey.ws> <51DB8639.9050906@ozlabs.ru> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 02/17] pseries: rework XICS List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexey Kardashevskiy Cc: Anthony Liguori , qemu-devel@nongnu.org, Alexander Graf , Paul Mackerras , Paolo Bonzini , qemu-ppc@nongnu.org, David Gibson On Tue, 2013-07-09 at 13:40 +1000, Alexey Kardashevskiy wrote: > No, why? It is a per CPU state of XICS controller, never exists apart > from XICS. ICP is. ICS is ... different but can mostly be considered to be the XICS itself. Anthony, we could be completely anal about it and create a gigantic cathedral of devices or just be a bit realistic and do something simpler that has the exact same functionality :) Basically, in HW the layout of the interrupt network is: - One ICP per processor thread (the "presenter"). This contains the registers to fetch a pending interrupt (ack), EOI, and control the processor priority. - One ICS per logical source of interrupts (ie, one per PCI host bridge, and a few others here or there). This contains the per-interrupt source configuration (target processor(s), priority, mask) and the per-interrupt internal state. Under PAPR, there is a single "virtual" ICS ... somewhat (it's a bit oddball what pHyp does here, arguably there are two but we can ignore that distinction). There is no register level access. A pair of firmware (RTAS) calls is used to configure each virtual interrupt. So our model here is somewhat the same. We have one ICS in the emulated XICS which arguably *is* the emulated XICS, there's no point making it a separate "device", that would just be gross, and each VCPU has an associated ICP. Cheers, Ben.