From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37262) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UwgKa-0001pp-Vj for qemu-devel@nongnu.org; Tue, 09 Jul 2013 18:24:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UwgKY-0002IA-1c for qemu-devel@nongnu.org; Tue, 09 Jul 2013 18:24:20 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Wed, 10 Jul 2013 00:23:25 +0200 Message-Id: <1373408640-6046-7-git-send-email-afaerber@suse.de> In-Reply-To: <1373408640-6046-1-git-send-email-afaerber@suse.de> References: <1373408640-6046-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH qom-cpu v3 06/41] cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Jia Liu , Anthony Green , Alexander Graf , Blue Swirl , Max Filippov , Michael Walle , "open list:PowerPC" , Paul Brook , "Edgar E. Iglesias" , Guan Xuetao , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno , Richard Henderson Where no extra implementation is needed, fall back to CPUClass::set_pc(). Acked-by: Michael Walle (for lm32) Signed-off-by: Andreas F=C3=A4rber --- cpu-exec.c | 8 +++++++- include/qom/cpu.h | 5 +++++ target-alpha/cpu.h | 5 ----- target-arm/cpu.h | 5 ----- target-cris/cpu.h | 4 ---- target-i386/cpu.c | 8 ++++++++ target-i386/cpu.h | 5 ----- target-lm32/cpu.h | 5 ----- target-m68k/cpu.h | 5 ----- target-microblaze/cpu.h | 5 ----- target-mips/cpu.c | 11 +++++++++++ target-mips/cpu.h | 7 ------- target-moxie/cpu.h | 5 ----- target-openrisc/cpu.h | 5 ----- target-ppc/cpu.h | 5 ----- target-s390x/cpu.h | 5 ----- target-sh4/cpu.c | 9 +++++++++ target-sh4/cpu.h | 6 ------ target-sparc/cpu.c | 9 +++++++++ target-sparc/cpu.h | 6 ------ target-unicore32/cpu.h | 5 ----- target-xtensa/cpu.h | 5 ----- 22 files changed, 49 insertions(+), 84 deletions(-) diff --git a/cpu-exec.c b/cpu-exec.c index 6c784a7..3fccb86 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -59,8 +59,14 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *c= pu, uint8_t *tb_ptr) * counter hit zero); we must restore the guest PC to the addres= s * of the start of the TB. */ + CPUClass *cc =3D CPU_GET_CLASS(cpu); TranslationBlock *tb =3D (TranslationBlock *)(next_tb & ~TB_EXIT= _MASK); - cpu_pc_from_tb(env, tb); + if (cc->synchronize_from_tb) { + cc->synchronize_from_tb(cpu, tb); + } else { + assert(cc->set_pc); + cc->set_pc(cpu, tb->pc); + } } if ((next_tb & TB_EXIT_MASK) =3D=3D TB_EXIT_REQUESTED) { /* We were asked to stop executing TBs (probably a pending diff --git a/include/qom/cpu.h b/include/qom/cpu.h index e4c1ed9..152dad5 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -56,6 +56,8 @@ typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwad= dr addr, bool is_write, bool is_exec, int opa= que, unsigned size); =20 +struct TranslationBlock; + /** * CPUClass: * @class_by_name: Callback to map -cpu command line model name to an @@ -70,6 +72,8 @@ typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwad= dr addr, * @get_paging_enabled: Callback for inquiring whether paging is enabled= . * @get_memory_mapping: Callback for obtaining the memory mappings. * @set_pc: Callback for setting the Program Counter register. + * @synchronize_from_tb: Callback for synchronizing state from a TCG + * #TranslationBlock. * @vmsd: State description for migration. * * Represents a CPU family or model. @@ -94,6 +98,7 @@ typedef struct CPUClass { void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); + void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *= tb); =20 const struct VMStateDescription *vmsd; int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index 066f032..c85dc6e 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -515,9 +515,4 @@ static inline bool cpu_has_work(CPUState *cpu) =20 #include "exec/exec-all.h" =20 -static inline void cpu_pc_from_tb(CPUAlphaState *env, TranslationBlock *= tb) -{ - env->pc =3D tb->pc; -} - #endif /* !defined (__CPU_ALPHA_H__) */ diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 1369604..0027492 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -796,11 +796,6 @@ static inline bool cpu_has_work(CPUState *cpu) =20 #include "exec/exec-all.h" =20 -static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb= ) -{ - env->regs[15] =3D tb->pc; -} - /* Load an instruction and return it in the standard little-endian order= */ static inline uint32_t arm_ldl_code(CPUARMState *env, uint32_t addr, bool do_swap) diff --git a/target-cris/cpu.h b/target-cris/cpu.h index c12a8ca..4b9fc4c 100644 --- a/target-cris/cpu.h +++ b/target-cris/cpu.h @@ -279,8 +279,4 @@ static inline bool cpu_has_work(CPUState *cpu) =20 #include "exec/exec-all.h" =20 -static inline void cpu_pc_from_tb(CPUCRISState *env, TranslationBlock *t= b) -{ - env->pc =3D tb->pc; -} #endif diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 67b095d..b57ea4b 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2513,6 +2513,13 @@ static void x86_cpu_set_pc(CPUState *cs, vaddr val= ue) cpu->env.eip =3D value; } =20 +static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *= tb) +{ + X86CPU *cpu =3D X86_CPU(cs); + + cpu->env.eip =3D tb->pc - tb->cs_base; +} + static void x86_cpu_common_class_init(ObjectClass *oc, void *data) { X86CPUClass *xcc =3D X86_CPU_CLASS(oc); @@ -2530,6 +2537,7 @@ static void x86_cpu_common_class_init(ObjectClass *= oc, void *data) cc->do_interrupt =3D x86_cpu_do_interrupt; cc->dump_state =3D x86_cpu_dump_state; cc->set_pc =3D x86_cpu_set_pc; + cc->synchronize_from_tb =3D x86_cpu_synchronize_from_tb; cc->get_arch_id =3D x86_cpu_get_arch_id; cc->get_paging_enabled =3D x86_cpu_get_paging_enabled; #ifndef CONFIG_USER_ONLY diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 2d005b3..cedefdc 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -1148,11 +1148,6 @@ static inline bool cpu_has_work(CPUState *cs) =20 #include "exec/exec-all.h" =20 -static inline void cpu_pc_from_tb(CPUX86State *env, TranslationBlock *tb= ) -{ - env->eip =3D tb->pc - tb->cs_base; -} - static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *= pc, target_ulong *cs_base, int *flag= s) { diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h index 856bdc7..dbfe043 100644 --- a/target-lm32/cpu.h +++ b/target-lm32/cpu.h @@ -232,9 +232,4 @@ static inline bool cpu_has_work(CPUState *cpu) =20 #include "exec/exec-all.h" =20 -static inline void cpu_pc_from_tb(CPULM32State *env, TranslationBlock *t= b) -{ - env->pc =3D tb->pc; -} - #endif diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h index 9fdf89e..cfd6846 100644 --- a/target-m68k/cpu.h +++ b/target-m68k/cpu.h @@ -260,9 +260,4 @@ static inline bool cpu_has_work(CPUState *cpu) =20 #include "exec/exec-all.h" =20 -static inline void cpu_pc_from_tb(CPUM68KState *env, TranslationBlock *t= b) -{ - env->pc =3D tb->pc; -} - #endif diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h index 6c35475..7508cf5 100644 --- a/target-microblaze/cpu.h +++ b/target-microblaze/cpu.h @@ -365,9 +365,4 @@ static inline bool cpu_has_work(CPUState *cpu) =20 #include "exec/exec-all.h" =20 -static inline void cpu_pc_from_tb(CPUMBState *env, TranslationBlock *tb) -{ - env->sregs[SR_PC] =3D tb->pc; -} - #endif diff --git a/target-mips/cpu.c b/target-mips/cpu.c index 6ec3d25..1581cd9 100644 --- a/target-mips/cpu.c +++ b/target-mips/cpu.c @@ -35,6 +35,16 @@ static void mips_cpu_set_pc(CPUState *cs, vaddr value) } } =20 +static void mips_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock = *tb) +{ + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + + env->active_tc.PC =3D tb->pc; + env->hflags &=3D ~MIPS_HFLAG_BMASK; + env->hflags |=3D tb->flags & MIPS_HFLAG_BMASK; +} + /* CPUClass::reset() */ static void mips_cpu_reset(CPUState *s) { @@ -90,6 +100,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *= data) cc->dump_state =3D mips_cpu_dump_state; cpu_class_set_do_unassigned_access(cc, mips_cpu_unassigned_access); cc->set_pc =3D mips_cpu_set_pc; + cc->synchronize_from_tb =3D mips_cpu_synchronize_from_tb; } =20 static const TypeInfo mips_cpu_type_info =3D { diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 7ffd2e3..a29c82f 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -732,13 +732,6 @@ static inline bool cpu_has_work(CPUState *cpu) =20 #include "exec/exec-all.h" =20 -static inline void cpu_pc_from_tb(CPUMIPSState *env, TranslationBlock *t= b) -{ - env->active_tc.PC =3D tb->pc; - env->hflags &=3D ~MIPS_HFLAG_BMASK; - env->hflags |=3D tb->flags & MIPS_HFLAG_BMASK; -} - static inline void compute_hflags(CPUMIPSState *env) { env->hflags &=3D ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0= | diff --git a/target-moxie/cpu.h b/target-moxie/cpu.h index 72d02c2..d5030a4 100644 --- a/target-moxie/cpu.h +++ b/target-moxie/cpu.h @@ -143,11 +143,6 @@ static inline int cpu_mmu_index(CPUMoxieState *env) #include "exec/cpu-all.h" #include "exec/exec-all.h" =20 -static inline void cpu_pc_from_tb(CPUMoxieState *env, TranslationBlock *= tb) -{ - env->pc =3D tb->pc; -} - static inline void cpu_get_tb_cpu_state(CPUMoxieState *env, target_ulong= *pc, target_ulong *cs_base, int *flag= s) { diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index 0aff8f2..82bfd03 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -428,9 +428,4 @@ static inline target_ulong cpu_get_pc(CPUOpenRISCStat= e *env) return env->pc; } =20 -static inline void cpu_pc_from_tb(CPUOpenRISCState *env, TranslationBloc= k *tb) -{ - env->pc =3D tb->pc; -} - #endif /* CPU_OPENRISC_H */ diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 7a7b1bf..6f51e1f 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -2144,11 +2144,6 @@ static inline bool cpu_has_work(CPUState *cpu) =20 #include "exec/exec-all.h" =20 -static inline void cpu_pc_from_tb(CPUPPCState *env, TranslationBlock *tb= ) -{ - env->nip =3D tb->pc; -} - void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env); =20 #endif /* !defined (__CPU_PPC_H__) */ diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h index 6462688..65bef86 100644 --- a/target-s390x/cpu.h +++ b/target-s390x/cpu.h @@ -1041,11 +1041,6 @@ static inline bool cpu_has_work(CPUState *cpu) (env->psw.mask & PSW_MASK_EXT); } =20 -static inline void cpu_pc_from_tb(CPUS390XState *env, TranslationBlock* = tb) -{ - env->psw.addr =3D tb->pc; -} - /* fpu_helper.c */ uint32_t set_cc_nz_f32(float32 v); uint32_t set_cc_nz_f64(float64 v); diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c index facbd18..03dedc1 100644 --- a/target-sh4/cpu.c +++ b/target-sh4/cpu.c @@ -31,6 +31,14 @@ static void superh_cpu_set_pc(CPUState *cs, vaddr valu= e) cpu->env.pc =3D value; } =20 +static void superh_cpu_synchronize_from_tb(CPUState *cs, TranslationBloc= k *tb) +{ + SuperHCPU *cpu =3D SUPERH_CPU(cs); + + cpu->env.pc =3D tb->pc; + cpu->env.flags =3D tb->flags; +} + /* CPUClass::reset() */ static void superh_cpu_reset(CPUState *s) { @@ -277,6 +285,7 @@ static void superh_cpu_class_init(ObjectClass *oc, vo= id *data) cc->do_interrupt =3D superh_cpu_do_interrupt; cc->dump_state =3D superh_cpu_dump_state; cc->set_pc =3D superh_cpu_set_pc; + cc->synchronize_from_tb =3D superh_cpu_synchronize_from_tb; dc->vmsd =3D &vmstate_sh_cpu; } =20 diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index c8df18b..276d295 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -359,10 +359,4 @@ static inline bool cpu_has_work(CPUState *cpu) =20 #include "exec/exec-all.h" =20 -static inline void cpu_pc_from_tb(CPUSH4State *env, TranslationBlock *tb= ) -{ - env->pc =3D tb->pc; - env->flags =3D tb->flags; -} - #endif /* _CPU_SH4_H */ diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c index 88582c6..a2deba5 100644 --- a/target-sparc/cpu.c +++ b/target-sparc/cpu.c @@ -731,6 +731,14 @@ static void sparc_cpu_set_pc(CPUState *cs, vaddr val= ue) cpu->env.npc =3D value + 4; } =20 +static void sparc_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock= *tb) +{ + SPARCCPU *cpu =3D SPARC_CPU(cs); + + cpu->env.pc =3D tb->pc; + cpu->env.npc =3D tb->cs_base; +} + static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) { SPARCCPUClass *scc =3D SPARC_CPU_GET_CLASS(dev); @@ -776,6 +784,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->dump_state =3D sparc_cpu_dump_state; cpu_class_set_do_unassigned_access(cc, sparc_cpu_unassigned_access); cc->set_pc =3D sparc_cpu_set_pc; + cc->synchronize_from_tb =3D sparc_cpu_synchronize_from_tb; } =20 static const TypeInfo sparc_cpu_type_info =3D { diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index 41b014a..0f35a22 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -759,10 +759,4 @@ static inline bool cpu_has_work(CPUState *cpu) =20 #include "exec/exec-all.h" =20 -static inline void cpu_pc_from_tb(CPUSPARCState *env, TranslationBlock *= tb) -{ - env->pc =3D tb->pc; - env->npc =3D tb->cs_base; -} - #endif diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h index d4be525..967511e 100644 --- a/target-unicore32/cpu.h +++ b/target-unicore32/cpu.h @@ -146,11 +146,6 @@ static inline int cpu_mmu_index(CPUUniCore32State *e= nv) #include "cpu-qom.h" #include "exec/exec-all.h" =20 -static inline void cpu_pc_from_tb(CPUUniCore32State *env, TranslationBlo= ck *tb) -{ - env->regs[31] =3D tb->pc; -} - static inline void cpu_get_tb_cpu_state(CPUUniCore32State *env, target_u= long *pc, target_ulong *cs_base, int *flag= s) { diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index 6c9fc35..a8f02f6 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -522,9 +522,4 @@ static inline int cpu_has_work(CPUState *cpu) return env->pending_irq_level; } =20 -static inline void cpu_pc_from_tb(CPUXtensaState *env, TranslationBlock = *tb) -{ - env->pc =3D tb->pc; -} - #endif --=20 1.8.1.4