From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33438) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UwvTk-0000E5-24 for qemu-devel@nongnu.org; Wed, 10 Jul 2013 10:35:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UwvTa-0003dW-07 for qemu-devel@nongnu.org; Wed, 10 Jul 2013 10:34:47 -0400 Received: from cantor2.suse.de ([195.135.220.15]:32793 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UwvTZ-0003ci-Nj for qemu-devel@nongnu.org; Wed, 10 Jul 2013 10:34:37 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Wed, 10 Jul 2013 16:34:02 +0200 Message-Id: <1373466860-32732-26-git-send-email-afaerber@suse.de> In-Reply-To: <1373466860-32732-1-git-send-email-afaerber@suse.de> References: <1373466860-32732-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PULL 25/43] target-arm: Change gen_intermediate_code_internal() argument to ARMCPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook Also use bool type while at it. Prepares for moving singlestep_enabled field to CPUState. Reviewed-by: Richard Henderson Signed-off-by: Andreas F=C3=A4rber --- target-arm/translate.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index af2aef2..9310c58 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -9796,10 +9796,11 @@ undef: /* generate intermediate code in gen_opc_buf and gen_opparam_buf for basic block 'tb'. If search_pc is TRUE, also generate PC information for each intermediate instruction. */ -static inline void gen_intermediate_code_internal(CPUARMState *env, +static inline void gen_intermediate_code_internal(ARMCPU *cpu, TranslationBlock *tb, - int search_pc) + bool search_pc) { + CPUARMState *env =3D &cpu->env; DisasContext dc1, *dc =3D &dc1; CPUBreakpoint *bp; uint16_t *gen_opc_end; @@ -10072,12 +10073,12 @@ done_generating: =20 void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb) { - gen_intermediate_code_internal(env, tb, 0); + gen_intermediate_code_internal(arm_env_get_cpu(env), tb, false); } =20 void gen_intermediate_code_pc(CPUARMState *env, TranslationBlock *tb) { - gen_intermediate_code_internal(env, tb, 1); + gen_intermediate_code_internal(arm_env_get_cpu(env), tb, true); } =20 static const char *cpu_mode_names[16] =3D { --=20 1.8.1.4