From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47035) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UyZPF-0005uC-W0 for qemu-devel@nongnu.org; Sun, 14 Jul 2013 23:24:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UyZPD-0005ta-Ew for qemu-devel@nongnu.org; Sun, 14 Jul 2013 23:24:57 -0400 Received: from mail-pd0-f172.google.com ([209.85.192.172]:56747) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UyZPD-0005tB-8Q for qemu-devel@nongnu.org; Sun, 14 Jul 2013 23:24:55 -0400 Received: by mail-pd0-f172.google.com with SMTP id z10so10273360pdj.31 for ; Sun, 14 Jul 2013 20:24:53 -0700 (PDT) From: Alexey Kardashevskiy Date: Mon, 15 Jul 2013 13:24:43 +1000 Message-Id: <1373858683-28415-1-git-send-email-aik@ozlabs.ru> Subject: [Qemu-devel] [PATCH] spapr-pci: remove io ports workaround List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Anthony Liguori , Alexey Kardashevskiy , Alexander Graf , qemu-ppc@nongnu.org, Paul Mackerras , David Gibson As it looks like all portio users have migrated to new portio api, the workaround with memory access to io ports routing is no more needed. This also fixes a bug with byte swapping as the io region was marked as little endian while it should not do any swapping at all. Signed-off-by: Alexey Kardashevskiy --- hw/ppc/spapr_pci.c | 52 +++------------------------------------------------- 1 file changed, 3 insertions(+), 49 deletions(-) diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index ca588aa..8d76290 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -440,43 +440,6 @@ static void pci_spapr_set_irq(void *opaque, int irq_num, int level) qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level); } -static uint64_t spapr_io_read(void *opaque, hwaddr addr, - unsigned size) -{ - switch (size) { - case 1: - return cpu_inb(addr); - case 2: - return cpu_inw(addr); - case 4: - return cpu_inl(addr); - } - g_assert_not_reached(); -} - -static void spapr_io_write(void *opaque, hwaddr addr, - uint64_t data, unsigned size) -{ - switch (size) { - case 1: - cpu_outb(addr, data); - return; - case 2: - cpu_outw(addr, data); - return; - case 4: - cpu_outl(addr, data); - return; - } - g_assert_not_reached(); -} - -static const MemoryRegionOps spapr_io_ops = { - .endianness = DEVICE_LITTLE_ENDIAN, - .read = spapr_io_read, - .write = spapr_io_write -}; - /* * MSI/MSIX memory region implementation. * The handler handles both MSI and MSIX. @@ -590,23 +553,14 @@ static int spapr_phb_init(SysBusDevice *s) memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr, &sphb->memwindow); - /* On ppc, we only have MMIO no specific IO space from the CPU - * perspective. In theory we ought to be able to embed the PCI IO - * memory region direction in the system memory space. However, - * if any of the IO BAR subregions use the old_portio mechanism, - * that won't be processed properly unless accessed from the - * system io address space. This hack to bounce things via - * system_io works around the problem until all the users of - * old_portion are updated */ + /* Initialize IO regions */ sprintf(namebuf, "%s.io", sphb->dtbusname); memory_region_init(&sphb->iospace, OBJECT(sphb), namebuf, SPAPR_PCI_IO_WIN_SIZE); - /* FIXME: fix to support multiple PHBs */ - memory_region_add_subregion(get_system_io(), 0, &sphb->iospace); sprintf(namebuf, "%s.io-alias", sphb->dtbusname); - memory_region_init_io(&sphb->iowindow, OBJECT(sphb), &spapr_io_ops, sphb, - namebuf, SPAPR_PCI_IO_WIN_SIZE); + memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), + namebuf, &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE); memory_region_add_subregion(get_system_memory(), sphb->io_win_addr, &sphb->iowindow); -- 1.8.3.2