From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35083) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UylZY-0003dC-94 for qemu-devel@nongnu.org; Mon, 15 Jul 2013 12:24:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UylZQ-0004zI-HM for qemu-devel@nongnu.org; Mon, 15 Jul 2013 12:24:24 -0400 Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa ([2001:8b0:1d0::1]:58665 helo=mnementh.archaic.org.uk) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UylZQ-0004x4-9o for qemu-devel@nongnu.org; Mon, 15 Jul 2013 12:24:16 -0400 From: Peter Maydell Date: Mon, 15 Jul 2013 17:01:32 +0100 Message-Id: <1373904095-27592-5-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1373904095-27592-1-git-send-email-peter.maydell@linaro.org> References: <1373904095-27592-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 4/7] hw/dma/omap_dma: Fix bugs with DMA requests above 32 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori Cc: qemu-devel@nongnu.org, Paul Brook The drqbmp field of struct soc_dma_s is a uint64_t; however several places in the code attempt to set bits in it using "(1 << drq)", which will fail if drq is large enough that the 1 bit gets shifted off the top of a 32 bit integer. Change these to "(1ULL << drq)" so that the promotion to 64 bit happens before the shift rather than afterwards. Signed-off-by: Peter Maydell Message-id: 1372423919-5669-1-git-send-email-peter.maydell@linaro.org --- hw/dma/omap_dma.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/hw/dma/omap_dma.c b/hw/dma/omap_dma.c index a81ffc4..0e8cccd 100644 --- a/hw/dma/omap_dma.c +++ b/hw/dma/omap_dma.c @@ -248,7 +248,7 @@ static void omap_dma_deactivate_channel(struct omap_dma_s *s, /* Don't deactive the channel if it is synchronized and the DMA request is active */ - if (ch->sync && ch->enable && (s->dma->drqbmp & (1 << ch->sync))) + if (ch->sync && ch->enable && (s->dma->drqbmp & (1ULL << ch->sync))) return; if (ch->active) { @@ -268,8 +268,9 @@ static void omap_dma_enable_channel(struct omap_dma_s *s, /* TODO: theoretically if ch->sync && ch->prefetch && * !s->dma->drqbmp[ch->sync], we should also activate and fetch * from source and then stall until signalled. */ - if ((!ch->sync) || (s->dma->drqbmp & (1 << ch->sync))) + if ((!ch->sync) || (s->dma->drqbmp & (1ULL << ch->sync))) { omap_dma_activate_channel(s, ch); + } } } @@ -1551,12 +1552,12 @@ static void omap_dma_request(void *opaque, int drq, int req) struct omap_dma_s *s = (struct omap_dma_s *) opaque; /* The request pins are level triggered in QEMU. */ if (req) { - if (~s->dma->drqbmp & (1 << drq)) { - s->dma->drqbmp |= 1 << drq; + if (~s->dma->drqbmp & (1ULL << drq)) { + s->dma->drqbmp |= 1ULL << drq; omap_dma_process_request(s, drq); } } else - s->dma->drqbmp &= ~(1 << drq); + s->dma->drqbmp &= ~(1ULL << drq); } /* XXX: this won't be needed once soc_dma knows about clocks. */ -- 1.7.9.5