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From: Peter Maydell <peter.maydell@linaro.org>
To: Aurelien Jarno <aurelien@aurel32.net>, Blue Swirl <blauwirbel@gmail.com>
Cc: Anthony Liguori <aliguori@us.ibm.com>,
	qemu-devel@nongnu.org, Paul Brook <paul@codesourcery.com>
Subject: [Qemu-devel] [PULL 4/8] target-arm/helper.c: OMAP/StrongARM cp15 crn=0 cleanup
Date: Mon, 15 Jul 2013 17:16:58 +0100	[thread overview]
Message-ID: <1373905022-27735-5-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1373905022-27735-1-git-send-email-peter.maydell@linaro.org>

From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

The if block detecting OMAP/StrongARM modifies the id_cp_reginfo
.access fields in place. So there is no need to replicate the call
to define_arm_cp_reg(). Dropped, and let the OMAP case fall through
to the normal behaviour after the in-place modification.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 72aae9b8ebbc9a76d2b06faf8666ef8a4b34b92a.1373429432.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/helper.c |   13 ++++---------
 1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 5f639fd..47e6c09 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1435,21 +1435,16 @@ void register_cp_regs_for_features(ARMCPU *cpu)
             arm_feature(env, ARM_FEATURE_STRONGARM)) {
             ARMCPRegInfo *r;
             /* Register the blanket "writes ignored" value first to cover the
-             * whole space. Then define the specific ID registers, but update
-             * their access field to allow write access, so that they ignore
-             * writes rather than causing them to UNDEF.
+             * whole space. Then update the specific ID registers to allow write
+             * access, so that they ignore writes rather than causing them to
+             * UNDEF.
              */
             define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
             for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
                 r->access = PL1_RW;
-                define_one_arm_cp_reg(cpu, r);
             }
-        } else {
-            /* Just register the standard ID registers (read-only, meaning
-             * that writes will UNDEF).
-             */
-            define_arm_cp_regs(cpu, id_cp_reginfo);
         }
+        define_arm_cp_regs(cpu, id_cp_reginfo);
     }
 
     if (arm_feature(env, ARM_FEATURE_AUXCR)) {
-- 
1.7.9.5

  parent reply	other threads:[~2013-07-15 16:24 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-07-15 16:16 [Qemu-devel] [PULL 0/8] target-arm queue Peter Maydell
2013-07-15 16:16 ` [Qemu-devel] [PULL 1/8] target-arm: add feature flag for ARMv8 Peter Maydell
2013-07-15 16:16 ` [Qemu-devel] [PULL 2/8] target-arm: implement LDA/STL instructions Peter Maydell
2013-07-15 16:16 ` [Qemu-devel] [PULL 3/8] target-arm: explicitly decode SEVL instruction Peter Maydell
2013-07-15 16:16 ` Peter Maydell [this message]
2013-07-15 16:16 ` [Qemu-devel] [PULL 5/8] target-arm/helper.c: Implement MIDR aliases Peter Maydell
2013-07-15 16:17 ` [Qemu-devel] [PULL 6/8] target-arm/helper.c: Allow const opaques in arm CP Peter Maydell
2013-07-15 16:17 ` [Qemu-devel] [PULL 7/8] target-arm: avoid undefined behaviour when writing TTBCR Peter Maydell
2013-07-15 16:17 ` [Qemu-devel] [PULL 8/8] target-arm: Avoid g_hash_table_get_keys() Peter Maydell

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