From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54403) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UypLi-0003DI-0c for qemu-devel@nongnu.org; Mon, 15 Jul 2013 16:26:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UypLe-000088-Ia for qemu-devel@nongnu.org; Mon, 15 Jul 2013 16:26:21 -0400 Received: from mail-qe0-x22a.google.com ([2607:f8b0:400d:c02::22a]:64281) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UypLe-00007w-EZ for qemu-devel@nongnu.org; Mon, 15 Jul 2013 16:26:18 -0400 Received: by mail-qe0-f42.google.com with SMTP id s14so6772210qeb.15 for ; Mon, 15 Jul 2013 13:26:18 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Mon, 15 Jul 2013 13:25:42 -0700 Message-Id: <1373919944-8521-2-git-send-email-rth@twiddle.net> In-Reply-To: <1373919944-8521-1-git-send-email-rth@twiddle.net> References: <1373919944-8521-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PULL 1/3] tcg/aarch64: implement ldst 12bit scaled uimm offset List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aliguori@us.ibm.com, Claudio Fontana , Richard Henderson From: Claudio Fontana implement the 12bit scaled unsigned immediate offset variant of LDR/STR. This improves code size by avoiding the movi + ldst_r for naturally aligned offsets in range. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 32 +++++++++++++++++++++++++++++--- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 562a549..cfd4081 100644 --- a/tcg/aarch64/tcg-target.c +++ b/tcg/aarch64/tcg-target.c @@ -315,6 +315,17 @@ static inline void tcg_out_ldst_9(TCGContext *s, tcg_out32(s, op_data << 24 | mod << 20 | off << 12 | rn << 5 | rd); } +/* tcg_out_ldst_12 expects a scaled unsigned immediate offset */ +static inline void tcg_out_ldst_12(TCGContext *s, + enum aarch64_ldst_op_data op_data, + enum aarch64_ldst_op_type op_type, + TCGReg rd, TCGReg rn, + tcg_target_ulong scaled_uimm) +{ + tcg_out32(s, (op_data | 1) << 24 + | op_type << 20 | scaled_uimm << 10 | rn << 5 | rd); +} + static inline void tcg_out_movr(TCGContext *s, int ext, TCGReg rd, TCGReg src) { /* register to register move using MOV (shifted register with no shift) */ @@ -374,10 +385,25 @@ static inline void tcg_out_ldst(TCGContext *s, enum aarch64_ldst_op_data data, { if (offset >= -256 && offset < 256) { tcg_out_ldst_9(s, data, type, rd, rn, offset); - } else { - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, offset); - tcg_out_ldst_r(s, data, type, rd, rn, TCG_REG_TMP); + return; } + + if (offset >= 256) { + /* if the offset is naturally aligned and in range, + then we can use the scaled uimm12 encoding */ + unsigned int s_bits = data >> 6; + if (!(offset & ((1 << s_bits) - 1))) { + tcg_target_ulong scaled_uimm = offset >> s_bits; + if (scaled_uimm <= 0xfff) { + tcg_out_ldst_12(s, data, type, rd, rn, scaled_uimm); + return; + } + } + } + + /* worst-case scenario, move offset to temp register, use reg offset */ + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, offset); + tcg_out_ldst_r(s, data, type, rd, rn, TCG_REG_TMP); } /* mov alias implemented with add immediate, useful to move to/from SP */ -- 1.8.3.1