From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35627) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V0sOr-0001Ep-NL for qemu-devel@nongnu.org; Sun, 21 Jul 2013 08:06:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V0sOq-0007ho-9F for qemu-devel@nongnu.org; Sun, 21 Jul 2013 08:06:05 -0400 Received: from mail-la0-x22d.google.com ([2a00:1450:4010:c03::22d]:62955) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V0sOp-0007hW-UR for qemu-devel@nongnu.org; Sun, 21 Jul 2013 08:06:04 -0400 Received: by mail-la0-f45.google.com with SMTP id ev20so2793632lab.4 for ; Sun, 21 Jul 2013 05:06:03 -0700 (PDT) From: Max Filippov Date: Sun, 21 Jul 2013 16:05:05 +0400 Message-Id: <1374408306-2684-6-git-send-email-jcmvbkbc@gmail.com> In-Reply-To: <1374408306-2684-1-git-send-email-jcmvbkbc@gmail.com> References: <1374408306-2684-1-git-send-email-jcmvbkbc@gmail.com> Subject: [Qemu-devel] [PATCH 5/6] target-xtensa: don't generate dead code to access invalid SRs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Blue Swirl , Max Filippov , Anthony Liguori This fixes the following test failure caused by access to undefined SR: qemu-system-xtensa -M sim -cpu dc232b -nographic -semihosting -kernel ./test_sr.tst QEMU 1.4.50 monitor - type 'help' for more information (qemu) QEMU 1.4.50 monitor - type 'help' for more information (qemu) qemu-system-xtensa: tcg/tcg.c:1673: temp_save: Assertion `s->temps[temp].val_type == 2 || s->temps[temp].fixed_reg' failed. Signed-off-by: Max Filippov --- target-xtensa/translate.c | 31 ++++++++++++++++++------------- 1 file changed, 18 insertions(+), 13 deletions(-) diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index ef97db0..dcd506f 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -491,7 +491,7 @@ static void gen_brcondi(DisasContext *dc, TCGCond cond, tcg_temp_free(tmp); } -static void gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access) +static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access) { if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) { if (sregnames[sr].name) { @@ -500,6 +500,7 @@ static void gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access) qemu_log("SR %d is not implemented\n", sr); } gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); + return false; } else if (!(sregnames[sr].access & access)) { static const char * const access_text[] = { [SR_R] = "rsr", @@ -510,7 +511,9 @@ static void gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access) qemu_log("SR %s is not available for %s\n", sregnames[sr].name, access_text[access]); gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); + return false; } + return true; } static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr) @@ -1482,9 +1485,9 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) break; case 6: /*XSR*/ - { + if (gen_check_sr(dc, RSR_SR, SR_X)) { TCGv_i32 tmp = tcg_temp_new_i32(); - gen_check_sr(dc, RSR_SR, SR_X); + if (RSR_SR >= 64) { gen_check_privilege(dc); } @@ -1707,21 +1710,23 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) case 3: /*RST3*/ switch (OP2) { case 0: /*RSR*/ - gen_check_sr(dc, RSR_SR, SR_R); - if (RSR_SR >= 64) { - gen_check_privilege(dc); + if (gen_check_sr(dc, RSR_SR, SR_R)) { + if (RSR_SR >= 64) { + gen_check_privilege(dc); + } + gen_window_check1(dc, RRR_T); + gen_rsr(dc, cpu_R[RRR_T], RSR_SR); } - gen_window_check1(dc, RRR_T); - gen_rsr(dc, cpu_R[RRR_T], RSR_SR); break; case 1: /*WSR*/ - gen_check_sr(dc, RSR_SR, SR_W); - if (RSR_SR >= 64) { - gen_check_privilege(dc); + if (gen_check_sr(dc, RSR_SR, SR_W)) { + if (RSR_SR >= 64) { + gen_check_privilege(dc); + } + gen_window_check1(dc, RRR_T); + gen_wsr(dc, RSR_SR, cpu_R[RRR_T]); } - gen_window_check1(dc, RRR_T); - gen_wsr(dc, RSR_SR, cpu_R[RRR_T]); break; case 2: /*SEXTu*/ -- 1.8.1.4