From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48723) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V1Ga5-0005go-MQ for qemu-devel@nongnu.org; Mon, 22 Jul 2013 09:55:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V1Ga1-0005wH-0L for qemu-devel@nongnu.org; Mon, 22 Jul 2013 09:55:17 -0400 Received: from mail-ee0-x231.google.com ([2a00:1450:4013:c00::231]:47534) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V1Ga0-0005vx-Qm for qemu-devel@nongnu.org; Mon, 22 Jul 2013 09:55:12 -0400 Received: by mail-ee0-f49.google.com with SMTP id b57so3778359eek.8 for ; Mon, 22 Jul 2013 06:55:12 -0700 (PDT) Sender: Paolo Bonzini From: Paolo Bonzini Date: Mon, 22 Jul 2013 15:54:20 +0200 Message-Id: <1374501278-31549-11-git-send-email-pbonzini@redhat.com> In-Reply-To: <1374501278-31549-1-git-send-email-pbonzini@redhat.com> References: <1374501278-31549-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PATCH 10/28] mipssim: do not use isa_mmio List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aliguori@us.ibm.com, aik@ozlabs.ru, agraf@suse.de, hpoussin@reactos.org, jan.kiszka@siemens.com, aurelien@aurel32.net Untested, this board does not support PCI so it cannot run endianness-test. It should fix endianness bugs in I/O port access. Signed-off-by: Paolo Bonzini --- hw/mips/mips_mipssim.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/mips/mips_mipssim.c b/hw/mips/mips_mipssim.c index a10cf13..e4a11c8 100644 --- a/hw/mips/mips_mipssim.c +++ b/hw/mips/mips_mipssim.c @@ -140,6 +140,7 @@ mips_mipssim_init(QEMUMachineInitArgs *args) const char *initrd_filename = args->initrd_filename; char *filename; MemoryRegion *address_space_mem = get_system_memory(); + MemoryRegion *isa = g_new(MemoryRegion, 1); MemoryRegion *ram = g_new(MemoryRegion, 1); MemoryRegion *bios = g_new(MemoryRegion, 1); MIPSCPU *cpu; @@ -212,7 +213,9 @@ mips_mipssim_init(QEMUMachineInitArgs *args) cpu_mips_clock_init(env); /* Register 64 KB of ISA IO space at 0x1fd00000. */ - isa_mmio_init(0x1fd00000, 0x00010000); + memory_region_init_alias(isa, NULL, "isa_mmio", + get_system_io(), 0, 0x00010000); + memory_region_add_subregion(get_system_memory(), 0x1fd00000, isa); /* A single 16450 sits at offset 0x3f8. It is attached to MIPS CPU INT2, which is interrupt 4. */ -- 1.8.1.4