From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40868) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V1SZb-00086E-7L for qemu-devel@nongnu.org; Mon, 22 Jul 2013 22:43:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V1SZa-0000qt-AW for qemu-devel@nongnu.org; Mon, 22 Jul 2013 22:43:35 -0400 Received: from cantor2.suse.de ([195.135.220.15]:49453 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V1SZa-0000qk-4T for qemu-devel@nongnu.org; Mon, 22 Jul 2013 22:43:34 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Tue, 23 Jul 2013 04:43:10 +0200 Message-Id: <1374547404-11700-3-git-send-email-afaerber@suse.de> In-Reply-To: <1374547404-11700-1-git-send-email-afaerber@suse.de> References: <1374547404-11700-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH v2 02/16] cpu/a9mpcore: Split off instance_init List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Paul Brook From: Andreas F=C3=A4rber Prepares for QOM realize. Signed-off-by: Andreas F=C3=A4rber --- hw/cpu/a9mpcore.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index 3e675e3..acbdab5 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -34,6 +34,14 @@ static void a9mp_priv_set_irq(void *opaque, int irq, i= nt level) qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); } =20 +static void a9mp_priv_initfn(Object *obj) +{ + A9MPPrivState *s =3D A9MPCORE_PRIV(obj); + + memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000= ); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container); +} + static int a9mp_priv_init(SysBusDevice *dev) { A9MPPrivState *s =3D A9MPCORE_PRIV(dev); @@ -78,7 +86,6 @@ static int a9mp_priv_init(SysBusDevice *dev) * * We should implement the global timer but don't currently do so. */ - memory_region_init(&s->container, OBJECT(s), "a9mp-priv-container", = 0x2000); memory_region_add_subregion(&s->container, 0, sysbus_mmio_get_region(scubusdev, 0)); /* GIC CPU interface */ @@ -94,8 +101,6 @@ static int a9mp_priv_init(SysBusDevice *dev) memory_region_add_subregion(&s->container, 0x1000, sysbus_mmio_get_region(gicbusdev, 0)); =20 - sysbus_init_mmio(dev, &s->container); - /* Wire up the interrupt from each watchdog and timer. * For each core the timer is PPI 29 and the watchdog PPI 30. */ @@ -134,6 +139,7 @@ static const TypeInfo a9mp_priv_info =3D { .name =3D TYPE_A9MPCORE_PRIV, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(A9MPPrivState), + .instance_init =3D a9mp_priv_initfn, .class_init =3D a9mp_priv_class_init, }; =20 --=20 1.8.1.4