From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40918) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V1SZd-00088V-V5 for qemu-devel@nongnu.org; Mon, 22 Jul 2013 22:43:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V1SZb-0000rU-Cv for qemu-devel@nongnu.org; Mon, 22 Jul 2013 22:43:37 -0400 Received: from cantor2.suse.de ([195.135.220.15]:49461 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V1SZb-0000rB-3G for qemu-devel@nongnu.org; Mon, 22 Jul 2013 22:43:35 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Tue, 23 Jul 2013 04:43:12 +0200 Message-Id: <1374547404-11700-5-git-send-email-afaerber@suse.de> In-Reply-To: <1374547404-11700-1-git-send-email-afaerber@suse.de> References: <1374547404-11700-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH v2 04/16] cpu/a9mpcore: Embed GICState List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Paul Brook From: Andreas F=C3=A4rber Prepares for conversion to QOM realize. Signed-off-by: Andreas F=C3=A4rber --- hw/cpu/a9mpcore.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index acbdab5..d157387 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -9,6 +9,7 @@ */ =20 #include "hw/sysbus.h" +#include "hw/intc/arm_gic.h" =20 #define TYPE_A9MPCORE_PRIV "a9mpcore_priv" #define A9MPCORE_PRIV(obj) \ @@ -23,15 +24,17 @@ typedef struct A9MPPrivState { MemoryRegion container; DeviceState *mptimer; DeviceState *wdt; - DeviceState *gic; DeviceState *scu; uint32_t num_irq; + + GICState gic; } A9MPPrivState; =20 static void a9mp_priv_set_irq(void *opaque, int irq, int level) { A9MPPrivState *s =3D (A9MPPrivState *)opaque; - qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); + + qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); } =20 static void a9mp_priv_initfn(Object *obj) @@ -40,19 +43,23 @@ static void a9mp_priv_initfn(Object *obj) =20 memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000= ); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container); + + object_initialize(&s->gic, TYPE_ARM_GIC); + qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); } =20 static int a9mp_priv_init(SysBusDevice *dev) { A9MPPrivState *s =3D A9MPCORE_PRIV(dev); + DeviceState *gicdev; SysBusDevice *timerbusdev, *wdtbusdev, *gicbusdev, *scubusdev; int i; =20 - s->gic =3D qdev_create(NULL, "arm_gic"); - qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); - qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); - qdev_init_nofail(s->gic); - gicbusdev =3D SYS_BUS_DEVICE(s->gic); + gicdev =3D DEVICE(&s->gic); + qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); + qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); + qdev_init_nofail(gicdev); + gicbusdev =3D SYS_BUS_DEVICE(&s->gic); =20 /* Pass through outbound IRQ lines from the GIC */ sysbus_pass_irq(dev, gicbusdev); @@ -107,9 +114,9 @@ static int a9mp_priv_init(SysBusDevice *dev) for (i =3D 0; i < s->num_cpu; i++) { int ppibase =3D (s->num_irq - 32) + i * 32; sysbus_connect_irq(timerbusdev, i, - qdev_get_gpio_in(s->gic, ppibase + 29)); + qdev_get_gpio_in(gicdev, ppibase + 29)); sysbus_connect_irq(wdtbusdev, i, - qdev_get_gpio_in(s->gic, ppibase + 30)); + qdev_get_gpio_in(gicdev, ppibase + 30)); } return 0; } --=20 1.8.1.4