From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43605) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V1Sjv-0004nE-NS for qemu-devel@nongnu.org; Mon, 22 Jul 2013 22:54:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V1Sjs-0005Hu-QF for qemu-devel@nongnu.org; Mon, 22 Jul 2013 22:54:15 -0400 Received: from cantor2.suse.de ([195.135.220.15]:49778 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V1Sjs-0005Hg-JB for qemu-devel@nongnu.org; Mon, 22 Jul 2013 22:54:12 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Tue, 23 Jul 2013 04:53:42 +0200 Message-Id: <1374548036-14471-11-git-send-email-afaerber@suse.de> In-Reply-To: <1374548036-14471-1-git-send-email-afaerber@suse.de> References: <1374548036-14471-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PULL 10/24] target-alpha: Copy implver to DisasContext List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= , Richard Henderson From: Richard Henderson Which allows removing env from DisasContext. Signed-off-by: Richard Henderson Signed-off-by: Andreas F=C3=A4rber --- target-alpha/translate.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 6a1aad6..c298c06 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -38,7 +38,6 @@ typedef struct DisasContext DisasContext; struct DisasContext { struct TranslationBlock *tb; - CPUAlphaState *env; uint64_t pc; int mem_idx; =20 @@ -47,6 +46,9 @@ struct DisasContext { /* Current flush-to-zero setting for this TB. */ int tb_ftz; =20 + /* implver value for this CPU. */ + int implver; + bool singlestep_enabled; }; =20 @@ -2250,8 +2252,9 @@ static ExitStatus translate_one(DisasContext *ctx, = uint32_t insn) break; case 0x6C: /* IMPLVER */ - if (rc !=3D 31) - tcg_gen_movi_i64(cpu_ir[rc], ctx->env->implver); + if (rc !=3D 31) { + tcg_gen_movi_i64(cpu_ir[rc], ctx->implver); + } break; default: goto invalid_opc; @@ -3400,9 +3403,9 @@ static inline void gen_intermediate_code_internal(A= lphaCPU *cpu, gen_opc_end =3D tcg_ctx.gen_opc_buf + OPC_MAX_SIZE; =20 ctx.tb =3D tb; - ctx.env =3D env; ctx.pc =3D pc_start; ctx.mem_idx =3D cpu_mmu_index(env); + ctx.implver =3D env->implver; ctx.singlestep_enabled =3D env->singlestep_enabled; =20 /* ??? Every TB begins with unset rounding mode, to be initialized o= n --=20 1.8.1.4