From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43540) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V1Sjr-0004fy-OH for qemu-devel@nongnu.org; Mon, 22 Jul 2013 22:54:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V1Sjo-0005Fz-Nd for qemu-devel@nongnu.org; Mon, 22 Jul 2013 22:54:11 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Tue, 23 Jul 2013 04:53:36 +0200 Message-Id: <1374548036-14471-5-git-send-email-afaerber@suse.de> In-Reply-To: <1374548036-14471-1-git-send-email-afaerber@suse.de> References: <1374548036-14471-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PULL 04/24] cpu: Introduce CPUClass::set_pc() for gdb_set_cpu_pc() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Jia Liu , Alexander Graf , Blue Swirl , Max Filippov , Michael Walle , "open list:PowerPC" , Paul Brook , "Edgar E. Iglesias" , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno , Richard Henderson This moves setting the Program Counter from gdbstub into target code. Use vaddr type as upper-bound replacement for target_ulong. Signed-off-by: Andreas F=C3=A4rber --- gdbstub.c | 39 ++++++--------------------------------- include/qom/cpu.h | 2 ++ target-alpha/cpu.c | 8 ++++++++ target-arm/cpu.c | 8 ++++++++ target-cris/cpu.c | 8 ++++++++ target-i386/cpu.c | 8 ++++++++ target-lm32/cpu.c | 8 ++++++++ target-microblaze/cpu.c | 8 ++++++++ target-mips/cpu.c | 14 ++++++++++++++ target-openrisc/cpu.c | 8 ++++++++ target-ppc/translate_init.c | 8 ++++++++ target-s390x/cpu.c | 8 ++++++++ target-sh4/cpu.c | 8 ++++++++ target-sparc/cpu.c | 9 +++++++++ target-xtensa/cpu.c | 8 ++++++++ 15 files changed, 119 insertions(+), 33 deletions(-) diff --git a/gdbstub.c b/gdbstub.c index bdba19b..55d4756 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -2042,40 +2042,13 @@ static void gdb_breakpoint_remove_all(void) =20 static void gdb_set_cpu_pc(GDBState *s, target_ulong pc) { - cpu_synchronize_state(ENV_GET_CPU(s->c_cpu)); -#if defined(TARGET_I386) - s->c_cpu->eip =3D pc; -#elif defined (TARGET_PPC) - s->c_cpu->nip =3D pc; -#elif defined (TARGET_SPARC) - s->c_cpu->pc =3D pc; - s->c_cpu->npc =3D pc + 4; -#elif defined (TARGET_ARM) - s->c_cpu->regs[15] =3D pc; -#elif defined (TARGET_SH4) - s->c_cpu->pc =3D pc; -#elif defined (TARGET_MIPS) - s->c_cpu->active_tc.PC =3D pc & ~(target_ulong)1; - if (pc & 1) { - s->c_cpu->hflags |=3D MIPS_HFLAG_M16; - } else { - s->c_cpu->hflags &=3D ~(MIPS_HFLAG_M16); + CPUState *cpu =3D ENV_GET_CPU(s->c_cpu); + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + cpu_synchronize_state(cpu); + if (cc->set_pc) { + cc->set_pc(cpu, pc); } -#elif defined (TARGET_MICROBLAZE) - s->c_cpu->sregs[SR_PC] =3D pc; -#elif defined(TARGET_OPENRISC) - s->c_cpu->pc =3D pc; -#elif defined (TARGET_CRIS) - s->c_cpu->pc =3D pc; -#elif defined (TARGET_ALPHA) - s->c_cpu->pc =3D pc; -#elif defined (TARGET_S390X) - s->c_cpu->psw.addr =3D pc; -#elif defined (TARGET_LM32) - s->c_cpu->pc =3D pc; -#elif defined(TARGET_XTENSA) - s->c_cpu->pc =3D pc; -#endif } =20 static CPUArchState *find_cpu(uint32_t thread_id) diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 829fd45..4620fee 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -73,6 +73,7 @@ typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwad= dr addr, * @get_arch_id: Callback for getting architecture-dependent CPU ID. * @get_paging_enabled: Callback for inquiring whether paging is enabled= . * @get_memory_mapping: Callback for obtaining the memory mappings. + * @set_pc: Callback for setting the Program Counter register. * @vmsd: State description for migration. * * Represents a CPU family or model. @@ -96,6 +97,7 @@ typedef struct CPUClass { bool (*get_paging_enabled)(const CPUState *cpu); void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, Error **errp); + void (*set_pc)(CPUState *cpu, vaddr value); =20 const struct VMStateDescription *vmsd; int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c index 2670805..09bb7a8 100644 --- a/target-alpha/cpu.c +++ b/target-alpha/cpu.c @@ -24,6 +24,13 @@ #include "migration/vmstate.h" =20 =20 +static void alpha_cpu_set_pc(CPUState *cs, vaddr value) +{ + AlphaCPU *cpu =3D ALPHA_CPU(cs); + + cpu->env.pc =3D value; +} + static void alpha_cpu_realizefn(DeviceState *dev, Error **errp) { AlphaCPUClass *acc =3D ALPHA_CPU_GET_CLASS(dev); @@ -264,6 +271,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, voi= d *data) cc->do_interrupt =3D alpha_cpu_do_interrupt; cc->dump_state =3D alpha_cpu_dump_state; cpu_class_set_do_unassigned_access(cc, alpha_cpu_unassigned_access); + cc->set_pc =3D alpha_cpu_set_pc; device_class_set_vmsd(dc, &vmstate_alpha_cpu); } =20 diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 9f1696f..082bc12 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -25,6 +25,13 @@ #endif #include "sysemu/sysemu.h" =20 +static void arm_cpu_set_pc(CPUState *cs, vaddr value) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + + cpu->env.regs[15] =3D value; +} + static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) { /* Reset a single ARMCPRegInfo register */ @@ -816,6 +823,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->class_by_name =3D arm_cpu_class_by_name; cc->do_interrupt =3D arm_cpu_do_interrupt; cc->dump_state =3D arm_cpu_dump_state; + cc->set_pc =3D arm_cpu_set_pc; cpu_class_set_vmsd(cc, &vmstate_arm_cpu); } =20 diff --git a/target-cris/cpu.c b/target-cris/cpu.c index 2abb57f..b72fd98 100644 --- a/target-cris/cpu.c +++ b/target-cris/cpu.c @@ -26,6 +26,13 @@ #include "mmu.h" =20 =20 +static void cris_cpu_set_pc(CPUState *cs, vaddr value) +{ + CRISCPU *cpu =3D CRIS_CPU(cs); + + cpu->env.pc =3D value; +} + /* CPUClass::reset() */ static void cris_cpu_reset(CPUState *s) { @@ -247,6 +254,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void= *data) cc->class_by_name =3D cris_cpu_class_by_name; cc->do_interrupt =3D cris_cpu_do_interrupt; cc->dump_state =3D cris_cpu_dump_state; + cc->set_pc =3D cris_cpu_set_pc; } =20 static const TypeInfo cris_cpu_type_info =3D { diff --git a/target-i386/cpu.c b/target-i386/cpu.c index e3f75a8..67b095d 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2506,6 +2506,13 @@ static bool x86_cpu_get_paging_enabled(const CPUSt= ate *cs) return cpu->env.cr[0] & CR0_PG_MASK; } =20 +static void x86_cpu_set_pc(CPUState *cs, vaddr value) +{ + X86CPU *cpu =3D X86_CPU(cs); + + cpu->env.eip =3D value; +} + static void x86_cpu_common_class_init(ObjectClass *oc, void *data) { X86CPUClass *xcc =3D X86_CPU_CLASS(oc); @@ -2522,6 +2529,7 @@ static void x86_cpu_common_class_init(ObjectClass *= oc, void *data) =20 cc->do_interrupt =3D x86_cpu_do_interrupt; cc->dump_state =3D x86_cpu_dump_state; + cc->set_pc =3D x86_cpu_set_pc; cc->get_arch_id =3D x86_cpu_get_arch_id; cc->get_paging_enabled =3D x86_cpu_get_paging_enabled; #ifndef CONFIG_USER_ONLY diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c index 04327ac..8aa28b5 100644 --- a/target-lm32/cpu.c +++ b/target-lm32/cpu.c @@ -22,6 +22,13 @@ #include "qemu-common.h" =20 =20 +static void lm32_cpu_set_pc(CPUState *cs, vaddr value) +{ + LM32CPU *cpu =3D LM32_CPU(cs); + + cpu->env.pc =3D value; +} + /* CPUClass::reset() */ static void lm32_cpu_reset(CPUState *s) { @@ -79,6 +86,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) =20 cc->do_interrupt =3D lm32_cpu_do_interrupt; cc->dump_state =3D lm32_cpu_dump_state; + cc->set_pc =3D lm32_cpu_set_pc; cpu_class_set_vmsd(cc, &vmstate_lm32_cpu); } =20 diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c index dce1c7e..0a9bcfa 100644 --- a/target-microblaze/cpu.c +++ b/target-microblaze/cpu.c @@ -26,6 +26,13 @@ #include "migration/vmstate.h" =20 =20 +static void mb_cpu_set_pc(CPUState *cs, vaddr value) +{ + MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); + + cpu->env.sregs[SR_PC] =3D value; +} + /* CPUClass::reset() */ static void mb_cpu_reset(CPUState *s) { @@ -134,6 +141,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *= data) cc->do_interrupt =3D mb_cpu_do_interrupt; cc->dump_state =3D mb_cpu_dump_state; cpu_class_set_do_unassigned_access(cc, mb_cpu_unassigned_access); + cc->set_pc =3D mb_cpu_set_pc; dc->vmsd =3D &vmstate_mb_cpu; dc->props =3D mb_properties; } diff --git a/target-mips/cpu.c b/target-mips/cpu.c index 60a3faf..6ec3d25 100644 --- a/target-mips/cpu.c +++ b/target-mips/cpu.c @@ -22,6 +22,19 @@ #include "qemu-common.h" =20 =20 +static void mips_cpu_set_pc(CPUState *cs, vaddr value) +{ + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + + env->active_tc.PC =3D value & ~(target_ulong)1; + if (value & 1) { + env->hflags |=3D MIPS_HFLAG_M16; + } else { + env->hflags &=3D ~(MIPS_HFLAG_M16); + } +} + /* CPUClass::reset() */ static void mips_cpu_reset(CPUState *s) { @@ -76,6 +89,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->do_interrupt =3D mips_cpu_do_interrupt; cc->dump_state =3D mips_cpu_dump_state; cpu_class_set_do_unassigned_access(cc, mips_cpu_unassigned_access); + cc->set_pc =3D mips_cpu_set_pc; } =20 static const TypeInfo mips_cpu_type_info =3D { diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c index 6d40f1b..27ee9f4 100644 --- a/target-openrisc/cpu.c +++ b/target-openrisc/cpu.c @@ -20,6 +20,13 @@ #include "cpu.h" #include "qemu-common.h" =20 +static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) +{ + OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); + + cpu->env.pc =3D value; +} + /* CPUClass::reset() */ static void openrisc_cpu_reset(CPUState *s) { @@ -146,6 +153,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, = void *data) cc->class_by_name =3D openrisc_cpu_class_by_name; cc->do_interrupt =3D openrisc_cpu_do_interrupt; cc->dump_state =3D openrisc_cpu_dump_state; + cc->set_pc =3D openrisc_cpu_set_pc; device_class_set_vmsd(dc, &vmstate_openrisc_cpu); } =20 diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 79bfcd8..9ed7736 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -8322,6 +8322,13 @@ CpuDefinitionInfoList *arch_query_cpu_definitions(= Error **errp) return cpu_list; } =20 +static void ppc_cpu_set_pc(CPUState *cs, vaddr value) +{ + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + + cpu->env.nip =3D value; +} + /* CPUClass::reset() */ static void ppc_cpu_reset(CPUState *s) { @@ -8449,6 +8456,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->do_interrupt =3D ppc_cpu_do_interrupt; cc->dump_state =3D ppc_cpu_dump_state; cc->dump_statistics =3D ppc_cpu_dump_statistics; + cc->set_pc =3D ppc_cpu_set_pc; } =20 static const TypeInfo ppc_cpu_type_info =3D { diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c index 1ef2fc0..fe3cd8e 100644 --- a/target-s390x/cpu.c +++ b/target-s390x/cpu.c @@ -58,6 +58,13 @@ CpuDefinitionInfoList *arch_query_cpu_definitions(Erro= r **errp) } #endif =20 +static void s390_cpu_set_pc(CPUState *cs, vaddr value) +{ + S390CPU *cpu =3D S390_CPU(cs); + + cpu->env.psw.addr =3D value; +} + /* CPUClass::reset() */ static void s390_cpu_reset(CPUState *s) { @@ -165,6 +172,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void= *data) =20 cc->do_interrupt =3D s390_cpu_do_interrupt; cc->dump_state =3D s390_cpu_dump_state; + cc->set_pc =3D s390_cpu_set_pc; dc->vmsd =3D &vmstate_s390_cpu; } =20 diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c index 03487eb..facbd18 100644 --- a/target-sh4/cpu.c +++ b/target-sh4/cpu.c @@ -24,6 +24,13 @@ #include "migration/vmstate.h" =20 =20 +static void superh_cpu_set_pc(CPUState *cs, vaddr value) +{ + SuperHCPU *cpu =3D SUPERH_CPU(cs); + + cpu->env.pc =3D value; +} + /* CPUClass::reset() */ static void superh_cpu_reset(CPUState *s) { @@ -269,6 +276,7 @@ static void superh_cpu_class_init(ObjectClass *oc, vo= id *data) cc->class_by_name =3D superh_cpu_class_by_name; cc->do_interrupt =3D superh_cpu_do_interrupt; cc->dump_state =3D superh_cpu_dump_state; + cc->set_pc =3D superh_cpu_set_pc; dc->vmsd =3D &vmstate_sh_cpu; } =20 diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c index 87c3a50..88582c6 100644 --- a/target-sparc/cpu.c +++ b/target-sparc/cpu.c @@ -723,6 +723,14 @@ void sparc_cpu_dump_state(CPUState *cs, FILE *f, fpr= intf_function cpu_fprintf, cpu_fprintf(f, "\n"); } =20 +static void sparc_cpu_set_pc(CPUState *cs, vaddr value) +{ + SPARCCPU *cpu =3D SPARC_CPU(cs); + + cpu->env.pc =3D value; + cpu->env.npc =3D value + 4; +} + static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) { SPARCCPUClass *scc =3D SPARC_CPU_GET_CLASS(dev); @@ -767,6 +775,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->do_interrupt =3D sparc_cpu_do_interrupt; cc->dump_state =3D sparc_cpu_dump_state; cpu_class_set_do_unassigned_access(cc, sparc_cpu_unassigned_access); + cc->set_pc =3D sparc_cpu_set_pc; } =20 static const TypeInfo sparc_cpu_type_info =3D { diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c index 0488984..e3d742a 100644 --- a/target-xtensa/cpu.c +++ b/target-xtensa/cpu.c @@ -33,6 +33,13 @@ #include "migration/vmstate.h" =20 =20 +static void xtensa_cpu_set_pc(CPUState *cs, vaddr value) +{ + XtensaCPU *cpu =3D XTENSA_CPU(cs); + + cpu->env.pc =3D value; +} + /* CPUClass::reset() */ static void xtensa_cpu_reset(CPUState *s) { @@ -100,6 +107,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, vo= id *data) =20 cc->do_interrupt =3D xtensa_cpu_do_interrupt; cc->dump_state =3D xtensa_cpu_dump_state; + cc->set_pc =3D xtensa_cpu_set_pc; dc->vmsd =3D &vmstate_xtensa_cpu; } =20 --=20 1.8.1.4