From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41551) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V1a8K-0001jo-KH for qemu-devel@nongnu.org; Tue, 23 Jul 2013 06:47:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V1a8I-0000lw-LX for qemu-devel@nongnu.org; Tue, 23 Jul 2013 06:47:56 -0400 Received: from mail-pb0-x22a.google.com ([2607:f8b0:400e:c01::22a]:49442) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V1a8I-0000li-Ej for qemu-devel@nongnu.org; Tue, 23 Jul 2013 06:47:54 -0400 Received: by mail-pb0-f42.google.com with SMTP id un1so8315001pbc.1 for ; Tue, 23 Jul 2013 03:47:53 -0700 (PDT) From: Jia Liu Date: Tue, 23 Jul 2013 18:47:35 +0800 Message-Id: <1374576458-22808-1-git-send-email-proljc@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="utf-8" Subject: [Qemu-devel] [PULL 0/3] OpenRISC patch queue List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, aliguori@us.ibm.com, afaerber@suse.de, anthony@codemonkey.ws Hi Anthony, This is my OpenRISC patch queue, and myfirst time to send a pull requests, please pull. It fix OpenRISC CPU and sim broad: * Free typename in openrisc_cpu_class_by_name * Use stderr output in openrisc_sim.c * fixed a indent typo. The following changes since commit 3464700f6aecb3e2aa9098839d90672d6b3fa974: tests: Add test-bitops.c with some sextract tests (2013-07-22 15:41:49 -0500) are available in the git repository at: git://github.com/J-Liu/qemu.git or32 for you to fetch changes up to 9b146e9a28bbd9567f5ac6a8e2bcb543aa3b9392: target-openrisc: Free typename in openrisc_cpu_class_by_name (2013-07-23 18:32:30 +0800) ---------------------------------------------------------------- Jia Liu (3): hw/openrisc: Indent typo hw/openrisc: Use stderr output instead of qemu_log target-openrisc: Free typename in openrisc_cpu_class_by_name hw/openrisc/openrisc_sim.c | 6 +++--- target-openrisc/cpu.c | 1 + 2 files changed, 4 insertions(+), 3 deletions(-)