From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46579) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V1jvl-0005dk-Ch for qemu-devel@nongnu.org; Tue, 23 Jul 2013 17:15:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V1jvh-00057K-QU for qemu-devel@nongnu.org; Tue, 23 Jul 2013 17:15:37 -0400 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Date: Tue, 23 Jul 2013 23:16:46 +0200 Message-Id: <1374614206-9368-3-git-send-email-hpoussin@reactos.org> In-Reply-To: <1374614206-9368-1-git-send-email-hpoussin@reactos.org> References: <1374614206-9368-1-git-send-email-hpoussin@reactos.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 2/2] i82378: cleanup implementation List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Herv=C3=A9=20Poussineau?= , =?UTF-8?q?Andreas=20F=C3=A4rber?= , qemu-ppc@nongnu.org - i82378 only exists on PCI bus ; do not split implementation in 2 struct= ures - remove BARs, which are not specified in datasheet - replace custom isa_mmio implementation by PCI bus IO region usage - use QOM casts when required Signed-off-by: Herv=C3=A9 Poussineau --- hw/isa/i82378.c | 220 ++++++++++++-------------------------------------= ------ 1 file changed, 48 insertions(+), 172 deletions(-) diff --git a/hw/isa/i82378.c b/hw/isa/i82378.c index de71d81..f2045de 100644 --- a/hw/isa/i82378.c +++ b/hw/isa/i82378.c @@ -22,134 +22,27 @@ #include "hw/timer/i8254.h" #include "hw/audio/pcspk.h" =20 -//#define DEBUG_I82378 - -#ifdef DEBUG_I82378 -#define DPRINTF(fmt, ...) \ -do { fprintf(stderr, "i82378: " fmt , ## __VA_ARGS__); } while (0) -#else -#define DPRINTF(fmt, ...) \ -do {} while (0) -#endif - -#define BADF(fmt, ...) \ -do { fprintf(stderr, "i82378 ERROR: " fmt , ## __VA_ARGS__); } while (0) +#define TYPE_I82378 "i82378" +#define I82378(obj) \ + OBJECT_CHECK(I82378State, (obj), TYPE_I82378) =20 typedef struct I82378State { + PCIDevice parent_obj; qemu_irq out[2]; qemu_irq *i8259; MemoryRegion io; - MemoryRegion mem; } I82378State; =20 -typedef struct PCIi82378State { - PCIDevice pci_dev; - uint32_t isa_io_base; - I82378State state; -} PCIi82378State; - -static const VMStateDescription vmstate_pci_i82378 =3D { - .name =3D "pci-i82378", +static const VMStateDescription vmstate_i82378 =3D { + .name =3D "i82378", .version_id =3D 0, .minimum_version_id =3D 0, .fields =3D (VMStateField[]) { - VMSTATE_PCI_DEVICE(pci_dev, PCIi82378State), + VMSTATE_PCI_DEVICE(parent_obj, I82378State), VMSTATE_END_OF_LIST() }, }; =20 -static void i82378_io_write(void *opaque, hwaddr addr, - uint64_t value, unsigned int size) -{ - switch (size) { - case 1: - DPRINTF("%s: " TARGET_FMT_plx "=3D%02" PRIx64 "\n", __func__, - addr, value); - cpu_outb(addr, value); - break; - case 2: - DPRINTF("%s: " TARGET_FMT_plx "=3D%04" PRIx64 "\n", __func__, - addr, value); - cpu_outw(addr, value); - break; - case 4: - DPRINTF("%s: " TARGET_FMT_plx "=3D%08" PRIx64 "\n", __func__, - addr, value); - cpu_outl(addr, value); - break; - default: - abort(); - } -} - -static uint64_t i82378_io_read(void *opaque, hwaddr addr, - unsigned int size) -{ - DPRINTF("%s: " TARGET_FMT_plx "\n", __func__, addr); - switch (size) { - case 1: - return cpu_inb(addr); - case 2: - return cpu_inw(addr); - case 4: - return cpu_inl(addr); - default: - abort(); - } -} - -static const MemoryRegionOps i82378_io_ops =3D { - .read =3D i82378_io_read, - .write =3D i82378_io_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, -}; - -static void i82378_mem_write(void *opaque, hwaddr addr, - uint64_t value, unsigned int size) -{ - switch (size) { - case 1: - DPRINTF("%s: " TARGET_FMT_plx "=3D%02" PRIx64 "\n", __func__, - addr, value); - cpu_outb(addr, value); - break; - case 2: - DPRINTF("%s: " TARGET_FMT_plx "=3D%04" PRIx64 "\n", __func__, - addr, value); - cpu_outw(addr, value); - break; - case 4: - DPRINTF("%s: " TARGET_FMT_plx "=3D%08" PRIx64 "\n", __func__, - addr, value); - cpu_outl(addr, value); - break; - default: - abort(); - } -} - -static uint64_t i82378_mem_read(void *opaque, hwaddr addr, - unsigned int size) -{ - DPRINTF("%s: " TARGET_FMT_plx "\n", __func__, addr); - switch (size) { - case 1: - return cpu_inb(addr); - case 2: - return cpu_inw(addr); - case 4: - return cpu_inl(addr); - default: - abort(); - } -} - -static const MemoryRegionOps i82378_mem_ops =3D { - .read =3D i82378_mem_read, - .write =3D i82378_mem_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, -}; - static void i82378_request_out0_irq(void *opaque, int irq, int level) { I82378State *s =3D opaque; @@ -159,19 +52,36 @@ static void i82378_request_out0_irq(void *opaque, in= t irq, int level) static void i82378_request_pic_irq(void *opaque, int irq, int level) { DeviceState *dev =3D opaque; - PCIDevice *pci =3D DO_UPCAST(PCIDevice, qdev, dev); - PCIi82378State *s =3D DO_UPCAST(PCIi82378State, pci_dev, pci); - - qemu_set_irq(s->state.i8259[irq], level); + qemu_set_irq(I82378(dev)->i8259[irq], level); } =20 -static void i82378_init(DeviceState *dev, I82378State *s) +static void i82378_realize(DeviceState *dev, Error **errp) { - ISABus *isabus =3D ISA_BUS(qdev_get_child_bus(dev, "isa.0")); - ISADevice *pit; + PCIDevice *pci =3D PCI_DEVICE(dev); + I82378State *s =3D I82378(dev); + DeviceClass *dc; + uint8_t *pci_conf; + ISABus *isabus; ISADevice *isa; qemu_irq *out0_irq; =20 + dc =3D DEVICE_CLASS(object_class_get_parent(object_get_class(OBJECT(= dev)))); + assert(dc); + dc->realize(dev, errp); + if (error_is_set(errp)) { + return; + } + + pci_conf =3D pci->config; + pci_set_word(pci_conf + PCI_COMMAND, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTE= R); + pci_set_word(pci_conf + PCI_STATUS, + PCI_STATUS_DEVSEL_MEDIUM); + + pci_config_set_interrupt_pin(pci_conf, 1); /* interrupt pin 0 */ + + isabus =3D isa_bus_new(dev, pci_address_space_io(pci)); + /* This device has: 2 82C59 (irq) 1 82C54 (pit) @@ -182,9 +92,6 @@ static void i82378_init(DeviceState *dev, I82378State = *s) All devices accept byte access only, except timer */ =20 - qdev_init_gpio_out(dev, s->out, 2); - qdev_init_gpio_in(dev, i82378_request_pic_irq, 16); - /* Workaround the fact that i8259 is not qdev'ified... */ out0_irq =3D qemu_allocate_irqs(i82378_request_out0_irq, s, 1); =20 @@ -193,10 +100,10 @@ static void i82378_init(DeviceState *dev, I82378Sta= te *s) isa_bus_irqs(isabus, s->i8259); =20 /* 1 82C54 (pit) */ - pit =3D pit_init(isabus, 0x40, 0, NULL); + isa =3D pit_init(isabus, 0x40, 0, NULL); =20 /* speaker */ - pcspk_init(isabus, pit); + pcspk_init(isabus, isa); =20 /* 2 82C37 (dma) */ isa =3D isa_create_simple(isabus, "i82374"); @@ -206,71 +113,40 @@ static void i82378_init(DeviceState *dev, I82378Sta= te *s) isa_create_simple(isabus, "mc146818rtc"); } =20 -static int pci_i82378_init(PCIDevice *dev) +static void i82378_instance_init(Object *obj) { - PCIi82378State *pci =3D DO_UPCAST(PCIi82378State, pci_dev, dev); - I82378State *s =3D &pci->state; - uint8_t *pci_conf; - - pci_conf =3D dev->config; - pci_set_word(pci_conf + PCI_COMMAND, - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTE= R); - pci_set_word(pci_conf + PCI_STATUS, - PCI_STATUS_DEVSEL_MEDIUM); - - pci_conf[PCI_INTERRUPT_PIN] =3D 1; /* interrupt pin 0 */ - - memory_region_init_io(&s->io, OBJECT(pci), &i82378_io_ops, s, - "i82378-io", 0x00010000); - pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->io); - - memory_region_init_io(&s->mem, OBJECT(pci), &i82378_mem_ops, s, - "i82378-mem", 0x01000000); - pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem); - - /* Make I/O address read only */ - pci_set_word(dev->wmask + PCI_COMMAND, PCI_COMMAND_SPECIAL); - pci_set_long(dev->wmask + PCI_BASE_ADDRESS_0, 0); - pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, pci->isa_io_base); + DeviceState *dev =3D DEVICE(obj); + I82378State *s =3D I82378(obj); =20 - isa_bus_new(&dev->qdev, pci_address_space_io(dev)); - - i82378_init(&dev->qdev, s); - - return 0; + qdev_init_gpio_out(dev, s->out, 2); + qdev_init_gpio_in(dev, i82378_request_pic_irq, 16); } =20 -static Property i82378_properties[] =3D { - DEFINE_PROP_HEX32("iobase", PCIi82378State, isa_io_base, 0x80000000)= , - DEFINE_PROP_END_OF_LIST() -}; - -static void pci_i82378_class_init(ObjectClass *klass, void *data) +static void i82378_class_init(ObjectClass *klass, void *data) { PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); DeviceClass *dc =3D DEVICE_CLASS(klass); =20 - k->init =3D pci_i82378_init; k->vendor_id =3D PCI_VENDOR_ID_INTEL; k->device_id =3D PCI_DEVICE_ID_INTEL_82378; k->revision =3D 0x03; k->class_id =3D PCI_CLASS_BRIDGE_ISA; - k->subsystem_vendor_id =3D 0x0; - k->subsystem_id =3D 0x0; - dc->vmsd =3D &vmstate_pci_i82378; - dc->props =3D i82378_properties; + dc->realize =3D i82378_realize; + dc->vmsd =3D &vmstate_i82378; + dc->no_user =3D 1; } =20 -static const TypeInfo pci_i82378_info =3D { - .name =3D "i82378", +static const TypeInfo i82378_info =3D { + .name =3D TYPE_I82378, .parent =3D TYPE_PCI_DEVICE, - .instance_size =3D sizeof(PCIi82378State), - .class_init =3D pci_i82378_class_init, + .instance_size =3D sizeof(I82378State), + .instance_init =3D i82378_instance_init, + .class_init =3D i82378_class_init, }; =20 static void i82378_register_types(void) { - type_register_static(&pci_i82378_info); + type_register_static(&i82378_info); } =20 type_init(i82378_register_types) --=20 1.7.10.4