From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55656) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V2Onx-0000Ev-OF for qemu-devel@nongnu.org; Thu, 25 Jul 2013 12:54:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V2Onu-0006n8-5G for qemu-devel@nongnu.org; Thu, 25 Jul 2013 12:54:17 -0400 Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa ([2001:8b0:1d0::1]:58953 helo=mnementh.archaic.org.uk) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V2Ont-0006mY-R9 for qemu-devel@nongnu.org; Thu, 25 Jul 2013 12:54:14 -0400 From: Peter Maydell Date: Thu, 25 Jul 2013 17:42:03 +0100 Message-Id: <1374770523-6570-3-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1374770523-6570-1-git-send-email-peter.maydell@linaro.org> References: <1374770523-6570-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [RFC 2/2] arm_gic: Use new __private macro to mark private fields List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Alexander Graf , Anthony Liguori , =?UTF-8?q?Andreas=20F=C3=A4rber?= , patches@linaro.org Use the new __private macro infrastructure to mark private fields for the arm_gic classes. Signed-off-by: Peter Maydell --- hw/intc/arm_gic.c | 3 +++ hw/intc/arm_gic_common.c | 2 ++ hw/intc/arm_gic_kvm.c | 2 ++ hw/intc/armv7m_nvic.c | 2 ++ include/hw/intc/arm_gic.h | 64 ++++++++++++++++++++++++++++----------------- 5 files changed, 49 insertions(+), 24 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 8e34004..cbe7d27 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -18,6 +18,9 @@ * armv7m_nvic device. */ +#define IMPLEMENTING_ARM_GIC_COMMON +#define IMPLEMENTING_ARM_GIC + #include "hw/sysbus.h" #include "gic_internal.h" #include "qom/cpu.h" diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index a89c786..c27c5c1 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -18,6 +18,8 @@ * with this program; if not, see . */ +#define IMPLEMENTING_ARM_GIC_COMMON + #include "gic_internal.h" static void gic_pre_save(void *opaque) diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c index f713975..0acd676 100644 --- a/hw/intc/arm_gic_kvm.c +++ b/hw/intc/arm_gic_kvm.c @@ -18,6 +18,8 @@ * with this program; if not, see . */ +#define IMPLEMENTING_ARM_GIC_COMMON + #include "hw/sysbus.h" #include "sysemu/kvm.h" #include "kvm_arm.h" diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 178344b..54d62fe 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -10,6 +10,8 @@ * NVIC. Much of that is also implemented here. */ +#define IMPLEMENTING_ARM_GIC_COMMON + #include "hw/sysbus.h" #include "qemu/timer.h" #include "hw/arm/arm.h" diff --git a/include/hw/intc/arm_gic.h b/include/hw/intc/arm_gic.h index be945ec..d978d72 100644 --- a/include/hw/intc/arm_gic.h +++ b/include/hw/intc/arm_gic.h @@ -40,36 +40,42 @@ typedef struct gic_irq_state { bool trigger; /* nonzero = edge triggered. */ } gic_irq_state; +#ifdef IMPLEMENTING_ARM_GIC_COMMON +#define __private +#else +#define __private QEMU_PRIVATE_ATTR +#endif + typedef struct GICState { /*< private >*/ - SysBusDevice busdev; + __private SysBusDevice busdev; /*< public >*/ - qemu_irq parent_irq[GIC_NCPU]; - bool enabled; - bool cpu_enabled[GIC_NCPU]; + __private qemu_irq parent_irq[GIC_NCPU]; + __private bool enabled; + __private bool cpu_enabled[GIC_NCPU]; - gic_irq_state irq_state[GIC_MAXIRQ]; - uint8_t irq_target[GIC_MAXIRQ]; - uint8_t priority1[GIC_INTERNAL][GIC_NCPU]; - uint8_t priority2[GIC_MAXIRQ - GIC_INTERNAL]; - uint16_t last_active[GIC_MAXIRQ][GIC_NCPU]; + __private gic_irq_state irq_state[GIC_MAXIRQ]; + __private uint8_t irq_target[GIC_MAXIRQ]; + __private uint8_t priority1[GIC_INTERNAL][GIC_NCPU]; + __private uint8_t priority2[GIC_MAXIRQ - GIC_INTERNAL]; + __private uint16_t last_active[GIC_MAXIRQ][GIC_NCPU]; - uint16_t priority_mask[GIC_NCPU]; - uint16_t running_irq[GIC_NCPU]; - uint16_t running_priority[GIC_NCPU]; - uint16_t current_pending[GIC_NCPU]; + __private uint16_t priority_mask[GIC_NCPU]; + __private uint16_t running_irq[GIC_NCPU]; + __private uint16_t running_priority[GIC_NCPU]; + __private uint16_t current_pending[GIC_NCPU]; - uint32_t num_cpu; + __private uint32_t num_cpu; - MemoryRegion iomem; /* Distributor */ + __private MemoryRegion iomem; /* Distributor */ /* This is just so we can have an opaque pointer which identifies * both this GIC and which CPU interface we should be accessing. */ - struct GICState *backref[GIC_NCPU]; - MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */ - uint32_t num_irq; - uint32_t revision; + __private struct GICState *backref[GIC_NCPU]; + __private MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */ + __private uint32_t num_irq; + __private uint32_t revision; } GICState; #define TYPE_ARM_GIC_COMMON "arm_gic_common" @@ -82,13 +88,21 @@ typedef struct GICState { typedef struct ARMGICCommonClass { /*< private >*/ - SysBusDeviceClass parent_class; + __private SysBusDeviceClass parent_class; /*< public >*/ - void (*pre_save)(GICState *s); - void (*post_load)(GICState *s); + __private void (*pre_save)(GICState *s); + __private void (*post_load)(GICState *s); } ARMGICCommonClass; +#undef __private + +#ifdef IMPLEMENTING_ARM_GIC +#define __private +#else +#define __private QEMU_PRIVATE_ATTR +#endif + #define TYPE_ARM_GIC "arm_gic" #define ARM_GIC(obj) \ OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC) @@ -99,10 +113,12 @@ typedef struct ARMGICCommonClass { typedef struct ARMGICClass { /*< private >*/ - ARMGICCommonClass parent_class; + __private ARMGICCommonClass parent_class; /*< public >*/ - DeviceRealize parent_realize; + __private DeviceRealize parent_realize; } ARMGICClass; +#undef __private + #endif -- 1.7.9.5