From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34152) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V2q9P-0008SJ-6X for qemu-devel@nongnu.org; Fri, 26 Jul 2013 18:06:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V2q9L-0002EA-FI for qemu-devel@nongnu.org; Fri, 26 Jul 2013 18:06:14 -0400 Received: from cantor2.suse.de ([195.135.220.15]:47391 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V2q9K-0002Dq-VA for qemu-devel@nongnu.org; Fri, 26 Jul 2013 18:06:11 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sat, 27 Jul 2013 00:05:38 +0200 Message-Id: <1374876350-32189-14-git-send-email-afaerber@suse.de> In-Reply-To: <1374876350-32189-1-git-send-email-afaerber@suse.de> References: <1374876350-32189-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PULL 13/25] target-mips: Move cpu_gdb_{read, write}_register() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno Signed-off-by: Andreas F=C3=A4rber --- gdbstub.c | 124 +------------------------------------------ target-mips/gdbstub.c | 144 ++++++++++++++++++++++++++++++++++++++++++++= ++++++ 2 files changed, 145 insertions(+), 123 deletions(-) create mode 100644 target-mips/gdbstub.c diff --git a/gdbstub.c b/gdbstub.c index 3ed2bfe..7ee0870 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -550,130 +550,8 @@ static int put_packet(GDBState *s, const char *buf) =20 #elif defined (TARGET_MIPS) =20 -static int cpu_gdb_read_register(CPUMIPSState *env, uint8_t *mem_buf, in= t n) -{ - if (n < 32) { - GET_REGL(env->active_tc.gpr[n]); - } - if (env->CP0_Config1 & (1 << CP0C1_FP)) { - if (n >=3D 38 && n < 70) { - if (env->CP0_Status & (1 << CP0St_FR)) { - GET_REGL(env->active_fpu.fpr[n - 38].d); - } else { - GET_REGL(env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]); - } - } - switch (n) { - case 70: - GET_REGL((int32_t)env->active_fpu.fcr31); - case 71: - GET_REGL((int32_t)env->active_fpu.fcr0); - } - } - switch (n) { - case 32: - GET_REGL((int32_t)env->CP0_Status); - case 33: - GET_REGL(env->active_tc.LO[0]); - case 34: - GET_REGL(env->active_tc.HI[0]); - case 35: - GET_REGL(env->CP0_BadVAddr); - case 36: - GET_REGL((int32_t)env->CP0_Cause); - case 37: - GET_REGL(env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16)); - case 72: - GET_REGL(0); /* fp */ - case 89: - GET_REGL((int32_t)env->CP0_PRid); - } - if (n >=3D 73 && n <=3D 88) { - /* 16 embedded regs. */ - GET_REGL(0); - } - - return 0; -} - -/* convert MIPS rounding mode in FCR31 to IEEE library */ -static unsigned int ieee_rm[] =3D { - float_round_nearest_even, - float_round_to_zero, - float_round_up, - float_round_down -}; -#define RESTORE_ROUNDING_MODE \ - set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], \ - &env->active_fpu.fp_status) - -static int cpu_gdb_write_register(CPUMIPSState *env, uint8_t *mem_buf, i= nt n) -{ - target_ulong tmp; - - tmp =3D ldtul_p(mem_buf); - - if (n < 32) { - env->active_tc.gpr[n] =3D tmp; - return sizeof(target_ulong); - } - if (env->CP0_Config1 & (1 << CP0C1_FP) - && n >=3D 38 && n < 73) { - if (n < 70) { - if (env->CP0_Status & (1 << CP0St_FR)) { - env->active_fpu.fpr[n - 38].d =3D tmp; - } else { - env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] =3D tmp; - } - } - switch (n) { - case 70: - env->active_fpu.fcr31 =3D tmp & 0xFF83FFFF; - /* set rounding mode */ - RESTORE_ROUNDING_MODE; - break; - case 71: - env->active_fpu.fcr0 =3D tmp; - break; - } - return sizeof(target_ulong); - } - switch (n) { - case 32: - env->CP0_Status =3D tmp; - break; - case 33: - env->active_tc.LO[0] =3D tmp; - break; - case 34: - env->active_tc.HI[0] =3D tmp; - break; - case 35: - env->CP0_BadVAddr =3D tmp; - break; - case 36: - env->CP0_Cause =3D tmp; - break; - case 37: - env->active_tc.PC =3D tmp & ~(target_ulong)1; - if (tmp & 1) { - env->hflags |=3D MIPS_HFLAG_M16; - } else { - env->hflags &=3D ~(MIPS_HFLAG_M16); - } - break; - case 72: /* fp, ignored */ - break; - default: - if (n > 89) { - return 0; - } - /* Other registers are readonly. Ignore writes. */ - break; - } +#include "target-mips/gdbstub.c" =20 - return sizeof(target_ulong); -} #elif defined(TARGET_OPENRISC) =20 static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf= , int n) diff --git a/target-mips/gdbstub.c b/target-mips/gdbstub.c new file mode 100644 index 0000000..15dc281 --- /dev/null +++ b/target-mips/gdbstub.c @@ -0,0 +1,144 @@ +/* + * MIPS gdb server stub + * + * Copyright (c) 2003-2005 Fabrice Bellard + * Copyright (c) 2013 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +static int cpu_gdb_read_register(CPUMIPSState *env, uint8_t *mem_buf, in= t n) +{ + if (n < 32) { + GET_REGL(env->active_tc.gpr[n]); + } + if (env->CP0_Config1 & (1 << CP0C1_FP)) { + if (n >=3D 38 && n < 70) { + if (env->CP0_Status & (1 << CP0St_FR)) { + GET_REGL(env->active_fpu.fpr[n - 38].d); + } else { + GET_REGL(env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]); + } + } + switch (n) { + case 70: + GET_REGL((int32_t)env->active_fpu.fcr31); + case 71: + GET_REGL((int32_t)env->active_fpu.fcr0); + } + } + switch (n) { + case 32: + GET_REGL((int32_t)env->CP0_Status); + case 33: + GET_REGL(env->active_tc.LO[0]); + case 34: + GET_REGL(env->active_tc.HI[0]); + case 35: + GET_REGL(env->CP0_BadVAddr); + case 36: + GET_REGL((int32_t)env->CP0_Cause); + case 37: + GET_REGL(env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16)); + case 72: + GET_REGL(0); /* fp */ + case 89: + GET_REGL((int32_t)env->CP0_PRid); + } + if (n >=3D 73 && n <=3D 88) { + /* 16 embedded regs. */ + GET_REGL(0); + } + + return 0; +} + +/* convert MIPS rounding mode in FCR31 to IEEE library */ +static unsigned int ieee_rm[] =3D { + float_round_nearest_even, + float_round_to_zero, + float_round_up, + float_round_down +}; +#define RESTORE_ROUNDING_MODE \ + set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], \ + &env->active_fpu.fp_status) + +static int cpu_gdb_write_register(CPUMIPSState *env, uint8_t *mem_buf, i= nt n) +{ + target_ulong tmp; + + tmp =3D ldtul_p(mem_buf); + + if (n < 32) { + env->active_tc.gpr[n] =3D tmp; + return sizeof(target_ulong); + } + if (env->CP0_Config1 & (1 << CP0C1_FP) + && n >=3D 38 && n < 73) { + if (n < 70) { + if (env->CP0_Status & (1 << CP0St_FR)) { + env->active_fpu.fpr[n - 38].d =3D tmp; + } else { + env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] =3D tmp; + } + } + switch (n) { + case 70: + env->active_fpu.fcr31 =3D tmp & 0xFF83FFFF; + /* set rounding mode */ + RESTORE_ROUNDING_MODE; + break; + case 71: + env->active_fpu.fcr0 =3D tmp; + break; + } + return sizeof(target_ulong); + } + switch (n) { + case 32: + env->CP0_Status =3D tmp; + break; + case 33: + env->active_tc.LO[0] =3D tmp; + break; + case 34: + env->active_tc.HI[0] =3D tmp; + break; + case 35: + env->CP0_BadVAddr =3D tmp; + break; + case 36: + env->CP0_Cause =3D tmp; + break; + case 37: + env->active_tc.PC =3D tmp & ~(target_ulong)1; + if (tmp & 1) { + env->hflags |=3D MIPS_HFLAG_M16; + } else { + env->hflags &=3D ~(MIPS_HFLAG_M16); + } + break; + case 72: /* fp, ignored */ + break; + default: + if (n > 89) { + return 0; + } + /* Other registers are readonly. Ignore writes. */ + break; + } + + return sizeof(target_ulong); +} --=20 1.8.1.4