From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34222) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V2q9T-0000BF-0Y for qemu-devel@nongnu.org; Fri, 26 Jul 2013 18:06:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V2q9O-0002Ft-0e for qemu-devel@nongnu.org; Fri, 26 Jul 2013 18:06:18 -0400 Received: from cantor2.suse.de ([195.135.220.15]:47401 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V2q9N-0002Fa-MW for qemu-devel@nongnu.org; Fri, 26 Jul 2013 18:06:13 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sat, 27 Jul 2013 00:05:43 +0200 Message-Id: <1374876350-32189-19-git-send-email-afaerber@suse.de> In-Reply-To: <1374876350-32189-1-git-send-email-afaerber@suse.de> References: <1374876350-32189-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PULL 18/25] target-alpha: Move cpu_gdb_{read, write}_register() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= , Richard Henderson Signed-off-by: Andreas F=C3=A4rber --- gdbstub.c | 66 +------------------------------------- target-alpha/gdbstub.c | 86 ++++++++++++++++++++++++++++++++++++++++++++= ++++++ 2 files changed, 87 insertions(+), 65 deletions(-) create mode 100644 target-alpha/gdbstub.c diff --git a/gdbstub.c b/gdbstub.c index 9ffb41f..51e64bb 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -570,72 +570,8 @@ static int put_packet(GDBState *s, const char *buf) =20 #elif defined (TARGET_ALPHA) =20 -static int cpu_gdb_read_register(CPUAlphaState *env, uint8_t *mem_buf, i= nt n) -{ - uint64_t val; - CPU_DoubleU d; - - switch (n) { - case 0 ... 30: - val =3D env->ir[n]; - break; - case 32 ... 62: - d.d =3D env->fir[n - 32]; - val =3D d.ll; - break; - case 63: - val =3D cpu_alpha_load_fpcr(env); - break; - case 64: - val =3D env->pc; - break; - case 66: - val =3D env->unique; - break; - case 31: - case 65: - /* 31 really is the zero register; 65 is unassigned in the - gdb protocol, but is still required to occupy 8 bytes. */ - val =3D 0; - break; - default: - return 0; - } - GET_REGL(val); -} +#include "target-alpha/gdbstub.c" =20 -static int cpu_gdb_write_register(CPUAlphaState *env, uint8_t *mem_buf, = int n) -{ - target_ulong tmp =3D ldtul_p(mem_buf); - CPU_DoubleU d; - - switch (n) { - case 0 ... 30: - env->ir[n] =3D tmp; - break; - case 32 ... 62: - d.ll =3D tmp; - env->fir[n - 32] =3D d.d; - break; - case 63: - cpu_alpha_store_fpcr(env, tmp); - break; - case 64: - env->pc =3D tmp; - break; - case 66: - env->unique =3D tmp; - break; - case 31: - case 65: - /* 31 really is the zero register; 65 is unassigned in the - gdb protocol, but is still required to occupy 8 bytes. */ - break; - default: - return 0; - } - return 8; -} #elif defined (TARGET_S390X) =20 static int cpu_gdb_read_register(CPUS390XState *env, uint8_t *mem_buf, i= nt n) diff --git a/target-alpha/gdbstub.c b/target-alpha/gdbstub.c new file mode 100644 index 0000000..b23afe4 --- /dev/null +++ b/target-alpha/gdbstub.c @@ -0,0 +1,86 @@ +/* + * Alpha gdb server stub + * + * Copyright (c) 2003-2005 Fabrice Bellard + * Copyright (c) 2013 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +static int cpu_gdb_read_register(CPUAlphaState *env, uint8_t *mem_buf, i= nt n) +{ + uint64_t val; + CPU_DoubleU d; + + switch (n) { + case 0 ... 30: + val =3D env->ir[n]; + break; + case 32 ... 62: + d.d =3D env->fir[n - 32]; + val =3D d.ll; + break; + case 63: + val =3D cpu_alpha_load_fpcr(env); + break; + case 64: + val =3D env->pc; + break; + case 66: + val =3D env->unique; + break; + case 31: + case 65: + /* 31 really is the zero register; 65 is unassigned in the + gdb protocol, but is still required to occupy 8 bytes. */ + val =3D 0; + break; + default: + return 0; + } + GET_REGL(val); +} + +static int cpu_gdb_write_register(CPUAlphaState *env, uint8_t *mem_buf, = int n) +{ + target_ulong tmp =3D ldtul_p(mem_buf); + CPU_DoubleU d; + + switch (n) { + case 0 ... 30: + env->ir[n] =3D tmp; + break; + case 32 ... 62: + d.ll =3D tmp; + env->fir[n - 32] =3D d.d; + break; + case 63: + cpu_alpha_store_fpcr(env, tmp); + break; + case 64: + env->pc =3D tmp; + break; + case 66: + env->unique =3D tmp; + break; + case 31: + case 65: + /* 31 really is the zero register; 65 is unassigned in the + gdb protocol, but is still required to occupy 8 bytes. */ + break; + default: + return 0; + } + return 8; +} --=20 1.8.1.4