From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57985) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V3oIM-0000cO-3I for qemu-devel@nongnu.org; Mon, 29 Jul 2013 10:19:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V3oI9-0000n6-Ft for qemu-devel@nongnu.org; Mon, 29 Jul 2013 10:19:30 -0400 Received: from e06smtp15.uk.ibm.com ([195.75.94.111]:47468) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V3oI9-0000mi-7u for qemu-devel@nongnu.org; Mon, 29 Jul 2013 10:19:17 -0400 Received: from /spool/local by e06smtp15.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Mon, 29 Jul 2013 15:14:00 +0100 Received: from b06cxnps3075.portsmouth.uk.ibm.com (d06relay10.portsmouth.uk.ibm.com [9.149.109.195]) by d06dlp03.portsmouth.uk.ibm.com (Postfix) with ESMTP id 5F8F01B0805D for ; Mon, 29 Jul 2013 15:19:14 +0100 (BST) Received: from d06av05.portsmouth.uk.ibm.com (d06av05.portsmouth.uk.ibm.com [9.149.37.229]) by b06cxnps3075.portsmouth.uk.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id r6TEJ2wf37159144 for ; Mon, 29 Jul 2013 14:19:02 GMT Received: from d06av05.portsmouth.uk.ibm.com (localhost [127.0.0.1]) by d06av05.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id r6TEJDqR005756 for ; Mon, 29 Jul 2013 08:19:13 -0600 From: Christian Borntraeger Date: Mon, 29 Jul 2013 16:19:24 +0200 Message-Id: <1375107567-24301-4-git-send-email-borntraeger@de.ibm.com> In-Reply-To: <1375107567-24301-1-git-send-email-borntraeger@de.ibm.com> References: <1375107567-24301-1-git-send-email-borntraeger@de.ibm.com> Subject: [Qemu-devel] [PATCH 3/6] s390: provide a cpu load normal function List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: Cornelia Huck , Christian Borntraeger , =?UTF-8?q?Andreas=20F=C3=A4rber?= , qemu-devel Some code needs to perform an IPL-like bootup that mimics the ESA (31bit) restart. Provide a cpu class method that does so. Signed-off-by: Christian Borntraeger --- target-s390x/cpu-qom.h | 2 ++ target-s390x/cpu.c | 10 ++++++++++ target-s390x/cpu.h | 3 +++ 3 files changed, 15 insertions(+) diff --git a/target-s390x/cpu-qom.h b/target-s390x/cpu-qom.h index cbe2341..2dc1750 100644 --- a/target-s390x/cpu-qom.h +++ b/target-s390x/cpu-qom.h @@ -36,6 +36,7 @@ * S390CPUClass: * @parent_realize: The parent class' realize handler. * @parent_reset: The parent class' reset handler. + * @load_normal: Performs a load normal. * * An S/390 CPU model. */ @@ -46,6 +47,7 @@ typedef struct S390CPUClass { DeviceRealize parent_realize; void (*parent_reset)(CPUState *cpu); + void (*load_normal)(CPUState *cpu); } S390CPUClass; /** diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c index a414750..0915c45 100644 --- a/target-s390x/cpu.c +++ b/target-s390x/cpu.c @@ -65,6 +65,15 @@ static void s390_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.psw.addr = value; } +/* CPUClass::load_normal() */ +static void s390_cpu_load_normal(CPUState *s) +{ + S390CPU *cpu = S390_CPU(s); + cpu->env.psw.addr = ldl_phys(4) & PSW_MASK_ESA_ADDR; + cpu->env.psw.mask = PSW_MASK_32 | PSW_MASK_64; + s390_add_running_cpu(cpu); +} + /* CPUClass::reset() */ static void s390_cpu_reset(CPUState *s) { @@ -168,6 +177,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data) dc->realize = s390_cpu_realizefn; scc->parent_reset = cc->reset; + scc->load_normal = s390_cpu_load_normal; cc->reset = s390_cpu_reset; cc->do_interrupt = s390_cpu_do_interrupt; diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h index 1c8e2c2..7ba4da2 100644 --- a/target-s390x/cpu.h +++ b/target-s390x/cpu.h @@ -228,6 +228,8 @@ typedef struct CPUS390XState { #undef PSW_MASK_CC #undef PSW_MASK_PM #undef PSW_MASK_64 +#undef PSW_MASK_32 +#undef PSW_MASK_ESA_ADDR #define PSW_MASK_PER 0x4000000000000000ULL #define PSW_MASK_DAT 0x0400000000000000ULL @@ -243,6 +245,7 @@ typedef struct CPUS390XState { #define PSW_MASK_PM 0x00000F0000000000ULL #define PSW_MASK_64 0x0000000100000000ULL #define PSW_MASK_32 0x0000000080000000ULL +#define PSW_MASK_ESA_ADDR 0x000000007fffffffULL #undef PSW_ASC_PRIMARY #undef PSW_ASC_ACCREG -- 1.8.3.1