From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55784) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V3t08-00029z-Ne for qemu-devel@nongnu.org; Mon, 29 Jul 2013 15:21:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V3t02-0002DG-Gp for qemu-devel@nongnu.org; Mon, 29 Jul 2013 15:21:00 -0400 Received: from cantor2.suse.de ([195.135.220.15]:53235 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V3t02-0002D7-75 for qemu-devel@nongnu.org; Mon, 29 Jul 2013 15:20:54 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Mon, 29 Jul 2013 21:17:56 +0200 Message-Id: <1375125630-24869-20-git-send-email-afaerber@suse.de> In-Reply-To: <1375125630-24869-1-git-send-email-afaerber@suse.de> References: <1375125630-24869-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PULL 019/173] pl041: Rename pl041_state to PL041State List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: "Vassili Karpov (malc)" , =?UTF-8?q?Andreas=20F=C3=A4rber?= Reviewed-by: Hu Tao [AF: Split off renaming from QOM cast changes] Signed-off-by: Andreas F=C3=A4rber --- hw/audio/pl041.c | 37 +++++++++++++++++++------------------ 1 file changed, 19 insertions(+), 18 deletions(-) diff --git a/hw/audio/pl041.c b/hw/audio/pl041.c index b66d6d2..c4d4f75 100644 --- a/hw/audio/pl041.c +++ b/hw/audio/pl041.c @@ -70,7 +70,7 @@ typedef struct { uint8_t rx_sample_size; } pl041_channel; =20 -typedef struct { +typedef struct PL041State { SysBusDevice busdev; MemoryRegion iomem; qemu_irq irq; @@ -80,7 +80,7 @@ typedef struct { pl041_regfile regs; pl041_channel fifo1; lm4549_state codec; -} pl041_state; +} PL041State; =20 =20 static const unsigned char pl041_default_id[8] =3D { @@ -107,7 +107,7 @@ static const char *get_reg_name(hwaddr offset) } #endif =20 -static uint8_t pl041_compute_periphid3(pl041_state *s) +static uint8_t pl041_compute_periphid3(PL041State *s) { uint8_t id3 =3D 1; /* One channel */ =20 @@ -142,7 +142,7 @@ static uint8_t pl041_compute_periphid3(pl041_state *s= ) return id3; } =20 -static void pl041_reset(pl041_state *s) +static void pl041_reset(PL041State *s) { DBG_L1("pl041_reset\n"); =20 @@ -156,7 +156,7 @@ static void pl041_reset(pl041_state *s) } =20 =20 -static void pl041_fifo1_write(pl041_state *s, uint32_t value) +static void pl041_fifo1_write(PL041State *s, uint32_t value) { pl041_channel *channel =3D &s->fifo1; pl041_fifo *fifo =3D &s->fifo1.tx_fifo; @@ -239,7 +239,7 @@ static void pl041_fifo1_write(pl041_state *s, uint32_= t value) DBG_L2("fifo1_push sr1 =3D 0x%08x\n", s->regs.sr1); } =20 -static void pl041_fifo1_transmit(pl041_state *s) +static void pl041_fifo1_transmit(PL041State *s) { pl041_channel *channel =3D &s->fifo1; pl041_fifo *fifo =3D &s->fifo1.tx_fifo; @@ -291,7 +291,7 @@ static void pl041_fifo1_transmit(pl041_state *s) } } =20 -static void pl041_isr1_update(pl041_state *s) +static void pl041_isr1_update(PL041State *s) { /* Update ISR1 */ if (s->regs.sr1 & TXUNDERRUN) { @@ -320,7 +320,7 @@ static void pl041_isr1_update(pl041_state *s) =20 static void pl041_request_data(void *opaque) { - pl041_state *s =3D (pl041_state *)opaque; + PL041State *s =3D (PL041State *)opaque; =20 /* Trigger pending transfers */ pl041_fifo1_transmit(s); @@ -330,7 +330,7 @@ static void pl041_request_data(void *opaque) static uint64_t pl041_read(void *opaque, hwaddr offset, unsigned size) { - pl041_state *s =3D (pl041_state *)opaque; + PL041State *s =3D (PL041State *)opaque; int value; =20 if ((offset >=3D PL041_periphid0) && (offset <=3D PL041_pcellid3)) { @@ -364,7 +364,7 @@ static uint64_t pl041_read(void *opaque, hwaddr offse= t, static void pl041_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { - pl041_state *s =3D (pl041_state *)opaque; + PL041State *s =3D (PL041State *)opaque; uint16_t control, data; uint32_t result; =20 @@ -504,7 +504,7 @@ static void pl041_write(void *opaque, hwaddr offset, =20 static void pl041_device_reset(DeviceState *d) { - pl041_state *s =3D DO_UPCAST(pl041_state, busdev.qdev, d); + PL041State *s =3D DO_UPCAST(PL041State, busdev.qdev, d); =20 pl041_reset(s); } @@ -517,7 +517,7 @@ static const MemoryRegionOps pl041_ops =3D { =20 static int pl041_init(SysBusDevice *dev) { - pl041_state *s =3D FROM_SYSBUS(pl041_state, dev); + PL041State *s =3D FROM_SYSBUS(PL041State, dev); =20 DBG_L1("pl041_init 0x%08x\n", (uint32_t)s); =20 @@ -603,12 +603,12 @@ static const VMStateDescription vmstate_pl041 =3D { .version_id =3D 1, .minimum_version_id =3D 1, .fields =3D (VMStateField[]) { - VMSTATE_UINT32(fifo_depth, pl041_state), - VMSTATE_STRUCT(regs, pl041_state, 0, + VMSTATE_UINT32(fifo_depth, PL041State), + VMSTATE_STRUCT(regs, PL041State, 0, vmstate_pl041_regfile, pl041_regfile), - VMSTATE_STRUCT(fifo1, pl041_state, 0, + VMSTATE_STRUCT(fifo1, PL041State, 0, vmstate_pl041_channel, pl041_channel), - VMSTATE_STRUCT(codec, pl041_state, 0, + VMSTATE_STRUCT(codec, PL041State, 0, vmstate_lm4549_state, lm4549_state), VMSTATE_END_OF_LIST() } @@ -616,7 +616,8 @@ static const VMStateDescription vmstate_pl041 =3D { =20 static Property pl041_device_properties[] =3D { /* Non-compact FIFO depth property */ - DEFINE_PROP_UINT32("nc_fifo_depth", pl041_state, fifo_depth, DEFAULT= _FIFO_DEPTH), + DEFINE_PROP_UINT32("nc_fifo_depth", PL041State, fifo_depth, + DEFAULT_FIFO_DEPTH), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -636,7 +637,7 @@ static void pl041_device_class_init(ObjectClass *klas= s, void *data) static const TypeInfo pl041_device_info =3D { .name =3D "pl041", .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(pl041_state), + .instance_size =3D sizeof(PL041State), .class_init =3D pl041_device_class_init, }; =20 --=20 1.8.1.4