From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55556) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V3szv-0001mJ-Q0 for qemu-devel@nongnu.org; Mon, 29 Jul 2013 15:20:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V3szp-00028W-9M for qemu-devel@nongnu.org; Mon, 29 Jul 2013 15:20:47 -0400 Received: from cantor2.suse.de ([195.135.220.15]:53192 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V3szo-00028I-L1 for qemu-devel@nongnu.org; Mon, 29 Jul 2013 15:20:41 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Mon, 29 Jul 2013 21:17:40 +0200 Message-Id: <1375125630-24869-4-git-send-email-afaerber@suse.de> In-Reply-To: <1375125630-24869-1-git-send-email-afaerber@suse.de> References: <1375125630-24869-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PULL 003/173] ide: Introduce abstract QOM type for PCIIDEState List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Kevin Wolf , =?UTF-8?q?Andreas=20F=C3=A4rber?= Needed for QOM casts. Signed-off-by: Andreas F=C3=A4rber --- hw/ide/cmd646.c | 62 ++++++++++++++++++++++++++++++---------------------= ------ hw/ide/pci.c | 30 +++++++++++++++++++++------- hw/ide/pci.h | 8 +++++++- hw/ide/piix.c | 24 ++++++++++------------ hw/ide/via.c | 18 ++++++++--------- 5 files changed, 82 insertions(+), 60 deletions(-) diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c index 33be386..d6ef799 100644 --- a/hw/ide/cmd646.c +++ b/hw/ide/cmd646.c @@ -127,7 +127,7 @@ static uint64_t bmdma_read(void *opaque, hwaddr addr, unsigned size) { BMDMAState *bm =3D opaque; - PCIIDEState *pci_dev =3D bm->pci_dev; + PCIDevice *pci_dev =3D PCI_DEVICE(bm->pci_dev); uint32_t val; =20 if (size !=3D 1) { @@ -139,16 +139,16 @@ static uint64_t bmdma_read(void *opaque, hwaddr add= r, val =3D bm->cmd; break; case 1: - val =3D pci_dev->dev.config[MRDMODE]; + val =3D pci_dev->config[MRDMODE]; break; case 2: val =3D bm->status; break; case 3: - if (bm =3D=3D &pci_dev->bmdma[0]) { - val =3D pci_dev->dev.config[UDIDETCR0]; + if (bm =3D=3D &bm->pci_dev->bmdma[0]) { + val =3D pci_dev->config[UDIDETCR0]; } else { - val =3D pci_dev->dev.config[UDIDETCR1]; + val =3D pci_dev->config[UDIDETCR1]; } break; default: @@ -165,7 +165,7 @@ static void bmdma_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { BMDMAState *bm =3D opaque; - PCIIDEState *pci_dev =3D bm->pci_dev; + PCIDevice *pci_dev =3D PCI_DEVICE(bm->pci_dev); =20 if (size !=3D 1) { return; @@ -179,18 +179,19 @@ static void bmdma_write(void *opaque, hwaddr addr, bmdma_cmd_writeb(bm, val); break; case 1: - pci_dev->dev.config[MRDMODE] =3D - (pci_dev->dev.config[MRDMODE] & ~0x30) | (val & 0x30); - cmd646_update_irq(pci_dev); + pci_dev->config[MRDMODE] =3D + (pci_dev->config[MRDMODE] & ~0x30) | (val & 0x30); + cmd646_update_irq(bm->pci_dev); break; case 2: bm->status =3D (val & 0x60) | (bm->status & 1) | (bm->status & ~= val & 0x06); break; case 3: - if (bm =3D=3D &pci_dev->bmdma[0]) - pci_dev->dev.config[UDIDETCR0] =3D val; - else - pci_dev->dev.config[UDIDETCR1] =3D val; + if (bm =3D=3D &bm->pci_dev->bmdma[0]) { + pci_dev->config[UDIDETCR0] =3D val; + } else { + pci_dev->config[UDIDETCR1] =3D val; + } break; } } @@ -222,25 +223,29 @@ static void bmdma_setup_bar(PCIIDEState *d) registers */ static void cmd646_update_irq(PCIIDEState *d) { + PCIDevice *pd =3D PCI_DEVICE(d); int pci_level; - pci_level =3D ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH0) && - !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH0)) || - ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH1) && - !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH1)); - qemu_set_irq(d->dev.irq[0], pci_level); + + pci_level =3D ((pd->config[MRDMODE] & MRDMODE_INTR_CH0) && + !(pd->config[MRDMODE] & MRDMODE_BLK_CH0)) || + ((pd->config[MRDMODE] & MRDMODE_INTR_CH1) && + !(pd->config[MRDMODE] & MRDMODE_BLK_CH1)); + qemu_set_irq(pd->irq[0], pci_level); } =20 /* the PCI irq level is the logical OR of the two channels */ static void cmd646_set_irq(void *opaque, int channel, int level) { PCIIDEState *d =3D opaque; + PCIDevice *pd =3D PCI_DEVICE(d); int irq_mask; =20 irq_mask =3D MRDMODE_INTR_CH0 << channel; - if (level) - d->dev.config[MRDMODE] |=3D irq_mask; - else - d->dev.config[MRDMODE] &=3D ~irq_mask; + if (level) { + pd->config[MRDMODE] |=3D irq_mask; + } else { + pd->config[MRDMODE] &=3D ~irq_mask; + } cmd646_update_irq(d); } =20 @@ -257,8 +262,8 @@ static void cmd646_reset(void *opaque) /* CMD646 PCI IDE controller */ static int pci_cmd646_ide_initfn(PCIDevice *dev) { - PCIIDEState *d =3D DO_UPCAST(PCIIDEState, dev, dev); - uint8_t *pci_conf =3D d->dev.config; + PCIIDEState *d =3D PCI_IDE(dev); + uint8_t *pci_conf =3D dev->config; qemu_irq *irq; int i; =20 @@ -284,7 +289,7 @@ static int pci_cmd646_ide_initfn(PCIDevice *dev) =20 irq =3D qemu_allocate_irqs(cmd646_set_irq, d, 2); for (i =3D 0; i < 2; i++) { - ide_bus_new(&d->bus[i], &d->dev.qdev, i, 2); + ide_bus_new(&d->bus[i], DEVICE(dev), i, 2); ide_init2(&d->bus[i], irq[i]); =20 bmdma_init(&d->bus[i], &d->bmdma[i], d); @@ -293,14 +298,14 @@ static int pci_cmd646_ide_initfn(PCIDevice *dev) &d->bmdma[i].dma); } =20 - vmstate_register(&dev->qdev, 0, &vmstate_ide_pci, d); + vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d); qemu_register_reset(cmd646_reset, d); return 0; } =20 static void pci_cmd646_ide_exitfn(PCIDevice *dev) { - PCIIDEState *d =3D DO_UPCAST(PCIIDEState, dev, dev); + PCIIDEState *d =3D PCI_IDE(dev); unsigned i; =20 for (i =3D 0; i < 2; ++i) { @@ -347,8 +352,7 @@ static void cmd646_ide_class_init(ObjectClass *klass,= void *data) =20 static const TypeInfo cmd646_ide_info =3D { .name =3D "cmd646-ide", - .parent =3D TYPE_PCI_DEVICE, - .instance_size =3D sizeof(PCIIDEState), + .parent =3D TYPE_PCI_IDE, .class_init =3D cmd646_ide_class_init, }; =20 diff --git a/hw/ide/pci.c b/hw/ide/pci.c index 635a364..91151fc 100644 --- a/hw/ide/pci.c +++ b/hw/ide/pci.c @@ -56,13 +56,14 @@ static int bmdma_prepare_buf(IDEDMA *dma, int is_writ= e) { BMDMAState *bm =3D DO_UPCAST(BMDMAState, dma, dma); IDEState *s =3D bmdma_active_if(bm); + PCIDevice *pci_dev =3D PCI_DEVICE(bm->pci_dev); struct { uint32_t addr; uint32_t size; } prd; int l, len; =20 - pci_dma_sglist_init(&s->sg, &bm->pci_dev->dev, + pci_dma_sglist_init(&s->sg, pci_dev, s->nsector / (BMDMA_PAGE_SIZE / 512) + 1); s->io_buffer_size =3D 0; for(;;) { @@ -71,7 +72,7 @@ static int bmdma_prepare_buf(IDEDMA *dma, int is_write) if (bm->cur_prd_last || (bm->cur_addr - bm->addr) >=3D BMDMA_PAGE_SIZE) return s->io_buffer_size !=3D 0; - pci_dma_read(&bm->pci_dev->dev, bm->cur_addr, &prd, 8); + pci_dma_read(pci_dev, bm->cur_addr, &prd, 8); bm->cur_addr +=3D 8; prd.addr =3D le32_to_cpu(prd.addr); prd.size =3D le32_to_cpu(prd.size); @@ -98,6 +99,7 @@ static int bmdma_rw_buf(IDEDMA *dma, int is_write) { BMDMAState *bm =3D DO_UPCAST(BMDMAState, dma, dma); IDEState *s =3D bmdma_active_if(bm); + PCIDevice *pci_dev =3D PCI_DEVICE(bm->pci_dev); struct { uint32_t addr; uint32_t size; @@ -113,7 +115,7 @@ static int bmdma_rw_buf(IDEDMA *dma, int is_write) if (bm->cur_prd_last || (bm->cur_addr - bm->addr) >=3D BMDMA_PAGE_SIZE) return 0; - pci_dma_read(&bm->pci_dev->dev, bm->cur_addr, &prd, 8); + pci_dma_read(pci_dev, bm->cur_addr, &prd, 8); bm->cur_addr +=3D 8; prd.addr =3D le32_to_cpu(prd.addr); prd.size =3D le32_to_cpu(prd.size); @@ -128,10 +130,10 @@ static int bmdma_rw_buf(IDEDMA *dma, int is_write) l =3D bm->cur_prd_len; if (l > 0) { if (is_write) { - pci_dma_write(&bm->pci_dev->dev, bm->cur_prd_addr, + pci_dma_write(pci_dev, bm->cur_prd_addr, s->io_buffer + s->io_buffer_index, l); } else { - pci_dma_read(&bm->pci_dev->dev, bm->cur_prd_addr, + pci_dma_read(pci_dev, bm->cur_prd_addr, s->io_buffer + s->io_buffer_index, l); } bm->cur_prd_addr +=3D l; @@ -480,7 +482,7 @@ const VMStateDescription vmstate_ide_pci =3D { .minimum_version_id_old =3D 0, .post_load =3D ide_pci_post_load, .fields =3D (VMStateField []) { - VMSTATE_PCI_DEVICE(dev, PCIIDEState), + VMSTATE_PCI_DEVICE(parent_obj, PCIIDEState), VMSTATE_STRUCT_ARRAY(bmdma, PCIIDEState, 2, 0, vmstate_bmdma, BMDMAState), VMSTATE_IDE_BUS_ARRAY(bus, PCIIDEState, 2), @@ -492,7 +494,7 @@ const VMStateDescription vmstate_ide_pci =3D { =20 void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table) { - PCIIDEState *d =3D DO_UPCAST(PCIIDEState, dev, dev); + PCIIDEState *d =3D PCI_IDE(dev); static const int bus[4] =3D { 0, 0, 1, 1 }; static const int unit[4] =3D { 0, 1, 0, 1 }; int i; @@ -531,3 +533,17 @@ void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDES= tate *d) bus->irq =3D *irq; bm->pci_dev =3D d; } + +static const TypeInfo pci_ide_type_info =3D { + .name =3D TYPE_PCI_IDE, + .parent =3D TYPE_PCI_DEVICE, + .instance_size =3D sizeof(PCIIDEState), + .abstract =3D true, +}; + +static void pci_ide_register_types(void) +{ + type_register_static(&pci_ide_type_info); +} + +type_init(pci_ide_register_types) diff --git a/hw/ide/pci.h b/hw/ide/pci.h index a694e54..2428275 100644 --- a/hw/ide/pci.h +++ b/hw/ide/pci.h @@ -37,8 +37,14 @@ typedef struct CMD646BAR { struct PCIIDEState *pci_dev; } CMD646BAR; =20 +#define TYPE_PCI_IDE "pci-ide" +#define PCI_IDE(obj) OBJECT_CHECK(PCIIDEState, (obj), TYPE_PCI_IDE) + typedef struct PCIIDEState { - PCIDevice dev; + /*< private >*/ + PCIDevice parent_obj; + /*< public >*/ + IDEBus bus[2]; BMDMAState bmdma[2]; uint32_t secondary; /* used only for cmd646 */ diff --git a/hw/ide/piix.c b/hw/ide/piix.c index 238e758..e6e6c0b 100644 --- a/hw/ide/piix.c +++ b/hw/ide/piix.c @@ -106,7 +106,8 @@ static void bmdma_setup_bar(PCIIDEState *d) static void piix3_reset(void *opaque) { PCIIDEState *d =3D opaque; - uint8_t *pci_conf =3D d->dev.config; + PCIDevice *pd =3D PCI_DEVICE(d); + uint8_t *pci_conf =3D pd->config; int i; =20 for (i =3D 0; i < 2; i++) { @@ -149,15 +150,15 @@ static void pci_piix_init_ports(PCIIDEState *d) { =20 static int pci_piix_ide_initfn(PCIDevice *dev) { - PCIIDEState *d =3D DO_UPCAST(PCIIDEState, dev, dev); - uint8_t *pci_conf =3D d->dev.config; + PCIIDEState *d =3D PCI_IDE(dev); + uint8_t *pci_conf =3D dev->config; =20 pci_conf[PCI_CLASS_PROG] =3D 0x80; // legacy ATA mode =20 qemu_register_reset(piix3_reset, d); =20 bmdma_setup_bar(d); - pci_register_bar(&d->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_ba= r); + pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); =20 vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d); =20 @@ -168,13 +169,11 @@ static int pci_piix_ide_initfn(PCIDevice *dev) =20 static int pci_piix3_xen_ide_unplug(DeviceState *dev) { - PCIDevice *pci_dev; PCIIDEState *pci_ide; DriveInfo *di; int i =3D 0; =20 - pci_dev =3D PCI_DEVICE(dev); - pci_ide =3D DO_UPCAST(PCIIDEState, dev, pci_dev); + pci_ide =3D PCI_IDE(dev); =20 for (; i < 3; i++) { di =3D drive_get_by_index(IF_IDE, i); @@ -203,7 +202,7 @@ PCIDevice *pci_piix3_xen_ide_init(PCIBus *bus, DriveI= nfo **hd_table, int devfn) =20 static void pci_piix_ide_exitfn(PCIDevice *dev) { - PCIIDEState *d =3D DO_UPCAST(PCIIDEState, dev, dev); + PCIIDEState *d =3D PCI_IDE(dev); unsigned i; =20 for (i =3D 0; i < 2; ++i) { @@ -254,8 +253,7 @@ static void piix3_ide_class_init(ObjectClass *klass, = void *data) =20 static const TypeInfo piix3_ide_info =3D { .name =3D "piix3-ide", - .parent =3D TYPE_PCI_DEVICE, - .instance_size =3D sizeof(PCIIDEState), + .parent =3D TYPE_PCI_IDE, .class_init =3D piix3_ide_class_init, }; =20 @@ -275,8 +273,7 @@ static void piix3_ide_xen_class_init(ObjectClass *kla= ss, void *data) =20 static const TypeInfo piix3_ide_xen_info =3D { .name =3D "piix3-ide-xen", - .parent =3D TYPE_PCI_DEVICE, - .instance_size =3D sizeof(PCIIDEState), + .parent =3D TYPE_PCI_IDE, .class_init =3D piix3_ide_xen_class_init, }; =20 @@ -297,8 +294,7 @@ static void piix4_ide_class_init(ObjectClass *klass, = void *data) =20 static const TypeInfo piix4_ide_info =3D { .name =3D "piix4-ide", - .parent =3D TYPE_PCI_DEVICE, - .instance_size =3D sizeof(PCIIDEState), + .parent =3D TYPE_PCI_IDE, .class_init =3D piix4_ide_class_init, }; =20 diff --git a/hw/ide/via.c b/hw/ide/via.c index d324884..e5fb297 100644 --- a/hw/ide/via.c +++ b/hw/ide/via.c @@ -108,7 +108,8 @@ static void bmdma_setup_bar(PCIIDEState *d) static void via_reset(void *opaque) { PCIIDEState *d =3D opaque; - uint8_t *pci_conf =3D d->dev.config; + PCIDevice *pd =3D PCI_DEVICE(d); + uint8_t *pci_conf =3D pd->config; int i; =20 for (i =3D 0; i < 2; i++) { @@ -158,7 +159,7 @@ static void vt82c686b_init_ports(PCIIDEState *d) { int i; =20 for (i =3D 0; i < 2; i++) { - ide_bus_new(&d->bus[i], &d->dev.qdev, i, 2); + ide_bus_new(&d->bus[i], DEVICE(d), i, 2); ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase, port_info[i].iobase2); ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq)); @@ -173,17 +174,17 @@ static void vt82c686b_init_ports(PCIIDEState *d) { /* via ide func */ static int vt82c686b_ide_initfn(PCIDevice *dev) { - PCIIDEState *d =3D DO_UPCAST(PCIIDEState, dev, dev); - uint8_t *pci_conf =3D d->dev.config; + PCIIDEState *d =3D PCI_IDE(dev); + uint8_t *pci_conf =3D dev->config; =20 pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy ATA mode */ pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); =20 qemu_register_reset(via_reset, d); bmdma_setup_bar(d); - pci_register_bar(&d->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_ba= r); + pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); =20 - vmstate_register(&dev->qdev, 0, &vmstate_ide_pci, d); + vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d); =20 vt82c686b_init_ports(d); =20 @@ -192,7 +193,7 @@ static int vt82c686b_ide_initfn(PCIDevice *dev) =20 static void vt82c686b_ide_exitfn(PCIDevice *dev) { - PCIIDEState *d =3D DO_UPCAST(PCIIDEState, dev, dev); + PCIIDEState *d =3D PCI_IDE(dev); unsigned i; =20 for (i =3D 0; i < 2; ++i) { @@ -229,8 +230,7 @@ static void via_ide_class_init(ObjectClass *klass, vo= id *data) =20 static const TypeInfo via_ide_info =3D { .name =3D "via-ide", - .parent =3D TYPE_PCI_DEVICE, - .instance_size =3D sizeof(PCIIDEState), + .parent =3D TYPE_PCI_IDE, .class_init =3D via_ide_class_init, }; =20 --=20 1.8.1.4