From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55612) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V3szy-0001oG-Uj for qemu-devel@nongnu.org; Mon, 29 Jul 2013 15:20:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V3szt-00029i-P7 for qemu-devel@nongnu.org; Mon, 29 Jul 2013 15:20:50 -0400 Received: from cantor2.suse.de ([195.135.220.15]:53209 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V3szt-00029X-C6 for qemu-devel@nongnu.org; Mon, 29 Jul 2013 15:20:45 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Mon, 29 Jul 2013 21:17:45 +0200 Message-Id: <1375125630-24869-9-git-send-email-afaerber@suse.de> In-Reply-To: <1375125630-24869-1-git-send-email-afaerber@suse.de> References: <1375125630-24869-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PULL 008/173] arm11mpcore: QOM cast cleanups for mpcore_rirq_state List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook Introduce a type constant, use QOM casts, rename the parent field and prepare for QOM realize. Reviewed-by: Hu Tao Signed-off-by: Andreas F=C3=A4rber --- hw/cpu/arm11mpcore.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu/arm11mpcore.c index 31c9d5a..a786c62 100644 --- a/hw/cpu/arm11mpcore.c +++ b/hw/cpu/arm11mpcore.c @@ -161,11 +161,16 @@ static int mpcore_priv_init(SysBusDevice *sbd) return 0; } =20 +#define TYPE_REALVIEW_MPCORE_RIRQ "realview_mpcore" +#define REALVIEW_MPCORE_RIRQ(obj) \ + OBJECT_CHECK(mpcore_rirq_state, (obj), TYPE_REALVIEW_MPCORE_RIRQ) + /* Dummy PIC to route IRQ lines. The baseboard has 4 independent IRQ controllers. The output of these, plus some of the raw input lines are fed into a single SMP-aware interrupt controller on the CPU. */ typedef struct { - SysBusDevice busdev; + SysBusDevice parent_obj; + SysBusDevice *priv; qemu_irq cpuic[32]; qemu_irq rvic[4][64]; @@ -196,9 +201,10 @@ static void mpcore_rirq_set_irq(void *opaque, int ir= q, int level) } } =20 -static int realview_mpcore_init(SysBusDevice *dev) +static int realview_mpcore_init(SysBusDevice *sbd) { - mpcore_rirq_state *s =3D FROM_SYSBUS(mpcore_rirq_state, dev); + DeviceState *dev =3D DEVICE(sbd); + mpcore_rirq_state *s =3D REALVIEW_MPCORE_RIRQ(dev); DeviceState *gic; DeviceState *priv; int n; @@ -208,7 +214,7 @@ static int realview_mpcore_init(SysBusDevice *dev) qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu); qdev_init_nofail(priv); s->priv =3D SYS_BUS_DEVICE(priv); - sysbus_pass_irq(dev, s->priv); + sysbus_pass_irq(sbd, s->priv); for (i =3D 0; i < 32; i++) { s->cpuic[i] =3D qdev_get_gpio_in(priv, i); } @@ -220,8 +226,8 @@ static int realview_mpcore_init(SysBusDevice *dev) s->rvic[n][i] =3D qdev_get_gpio_in(gic, i); } } - qdev_init_gpio_in(&dev->qdev, mpcore_rirq_set_irq, 64); - sysbus_init_mmio(dev, sysbus_mmio_get_region(s->priv, 0)); + qdev_init_gpio_in(dev, mpcore_rirq_set_irq, 64); + sysbus_init_mmio(sbd, sysbus_mmio_get_region(s->priv, 0)); return 0; } =20 @@ -240,7 +246,7 @@ static void mpcore_rirq_class_init(ObjectClass *klass= , void *data) } =20 static const TypeInfo mpcore_rirq_info =3D { - .name =3D "realview_mpcore", + .name =3D TYPE_REALVIEW_MPCORE_RIRQ, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(mpcore_rirq_state), .class_init =3D mpcore_rirq_class_init, --=20 1.8.1.4