[Qemu-devel] [PATCH for-next 0/4] target-ppc: Complete POWER5+ CPU model support

[Qemu-devel] [PATCH for-next 0/4] target-ppc: Complete POWER5+ CPU model support

[Andreas Färber]

Hello,

This mini-series cleans up, enables and complements POWER5+ support, so that
KVM with default -cpu host works on POWER5+ (gs) v2.1.

Thanks to Ben for some valuable hints on how to model POWER5P family!

Regards,
Andreas

Cc: Anthony Liguori <anthony@codemonkey.ws>
Cc: Alexey Kardashevskiy <aik@ozlabs.ru>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Alexander Graf <agraf@suse.de>
Cc: qemu-ppc@nongnu.org

Andreas Färber (4):
  target-ppc: Turn POWER5gs CPU into alias for POWER5+
  target-ppc: Turn POWER5gr CPU into alias for POWER5
  target-ppc: Prepare POWER5P CPU family
  target-ppc: Add POWER5+ v2.1 CPU model

 target-ppc/cpu-models.c     |  10 ++---
 target-ppc/cpu-models.h     |   3 +-
 target-ppc/translate_init.c | 104 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 109 insertions(+), 8 deletions(-)

-- 
1.8.1.4

[Qemu-devel] [PATCH for-next 1/4] target-ppc: Turn POWER5gs CPU into alias for POWER5+

[Andreas Färber]

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-ppc/cpu-models.c | 3 +--
 target-ppc/cpu-models.h | 1 -
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c
index 9578ed8..49b193f 100644
--- a/target-ppc/cpu-models.c
+++ b/target-ppc/cpu-models.c
@@ -1126,8 +1126,6 @@
 #if defined(TODO)
     POWERPC_DEF("POWER5+",       CPU_POWERPC_POWER5P,                POWER5P,
                 "POWER5+")
-    POWERPC_DEF("POWER5gs",      CPU_POWERPC_POWER5GS,               POWER5P,
-                "POWER5GS")
 #endif
 #if defined(TODO)
     POWERPC_DEF("POWER6",        CPU_POWERPC_POWER6,                 POWER6,
@@ -1389,6 +1387,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] = {
     { "Boxer", "POWER3" },
     { "Dino",  "POWER3" },
     { "POWER3+", "631" },
+    { "POWER5gs", "POWER5+" },
     { "POWER7", "POWER7_v2.3" },
     { "POWER8", "POWER8_v1.0" },
     { "970fx", "970fx_v3.1" },
diff --git a/target-ppc/cpu-models.h b/target-ppc/cpu-models.h
index 01e488f..0e4db11 100644
--- a/target-ppc/cpu-models.h
+++ b/target-ppc/cpu-models.h
@@ -549,7 +549,6 @@ enum {
     CPU_POWERPC_POWER5             = 0x003A0203,
 #define CPU_POWERPC_POWER5GR         CPU_POWERPC_POWER5
     CPU_POWERPC_POWER5P            = 0x003B0000,
-#define CPU_POWERPC_POWER5GS         CPU_POWERPC_POWER5P
     CPU_POWERPC_POWER6             = 0x003E0000,
     CPU_POWERPC_POWER6_5           = 0x0F000001, /* POWER6 in POWER5 mode */
     CPU_POWERPC_POWER6A            = 0x0F000002,
-- 
1.8.1.4

[Qemu-devel] [PATCH for-next 2/4] target-ppc: Turn POWER5gr CPU into alias for POWER5

[Andreas Färber]

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-ppc/cpu-models.c | 3 +--
 target-ppc/cpu-models.h | 1 -
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c
index 49b193f..3f7a6f4 100644
--- a/target-ppc/cpu-models.c
+++ b/target-ppc/cpu-models.c
@@ -1120,8 +1120,6 @@
 #if defined(TODO)
     POWERPC_DEF("POWER5",        CPU_POWERPC_POWER5,                 POWER5,
                 "POWER5")
-    POWERPC_DEF("POWER5gr",      CPU_POWERPC_POWER5GR,               POWER5,
-                "POWER5GR")
 #endif
 #if defined(TODO)
     POWERPC_DEF("POWER5+",       CPU_POWERPC_POWER5P,                POWER5P,
@@ -1387,6 +1385,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] = {
     { "Boxer", "POWER3" },
     { "Dino",  "POWER3" },
     { "POWER3+", "631" },
+    { "POWER5gr", "POWER5" },
     { "POWER5gs", "POWER5+" },
     { "POWER7", "POWER7_v2.3" },
     { "POWER8", "POWER8_v1.0" },
diff --git a/target-ppc/cpu-models.h b/target-ppc/cpu-models.h
index 0e4db11..a844d0d 100644
--- a/target-ppc/cpu-models.h
+++ b/target-ppc/cpu-models.h
@@ -547,7 +547,6 @@ enum {
     CPU_POWERPC_POWER4P            = 0x00380000,
      /* XXX: missing 0x003A0201 */
     CPU_POWERPC_POWER5             = 0x003A0203,
-#define CPU_POWERPC_POWER5GR         CPU_POWERPC_POWER5
     CPU_POWERPC_POWER5P            = 0x003B0000,
     CPU_POWERPC_POWER6             = 0x003E0000,
     CPU_POWERPC_POWER6_5           = 0x0F000001, /* POWER6 in POWER5 mode */
-- 
1.8.1.4

[Qemu-devel] [PATCH for-next 3/4] target-ppc: Prepare POWER5P CPU family

[Andreas Färber]

It is ISA 2.03. Modelled as 970FX minus AltiVec flag.

Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-ppc/cpu-models.c     |   2 -
 target-ppc/translate_init.c | 104 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 104 insertions(+), 2 deletions(-)

diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c
index 3f7a6f4..f2604eb 100644
--- a/target-ppc/cpu-models.c
+++ b/target-ppc/cpu-models.c
@@ -1121,10 +1121,8 @@
     POWERPC_DEF("POWER5",        CPU_POWERPC_POWER5,                 POWER5,
                 "POWER5")
 #endif
-#if defined(TODO)
     POWERPC_DEF("POWER5+",       CPU_POWERPC_POWER5P,                POWER5P,
                 "POWER5+")
-#endif
 #if defined(TODO)
     POWERPC_DEF("POWER6",        CPU_POWERPC_POWER6,                 POWER6,
                 "POWER6")
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index b14aec8..13b290c 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7023,6 +7023,110 @@ POWERPC_FAMILY(970MP)(ObjectClass *oc, void *data)
                  POWERPC_FLAG_BUS_CLK;
 }
 
+static void init_proc_power5plus(CPUPPCState *env)
+{
+    gen_spr_ne_601(env);
+    gen_spr_7xx(env);
+    /* Time base */
+    gen_tbl(env);
+    /* Hardware implementation registers */
+    /* XXX : not implemented */
+    spr_register(env, SPR_HID0, "HID0",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_read_generic, &spr_write_clear,
+                 0x60000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_HID1, "HID1",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_read_generic, &spr_write_generic,
+                 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_750FX_HID2, "HID2",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_read_generic, &spr_write_generic,
+                 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_970_HID5, "HID5",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_read_generic, &spr_write_generic,
+                 POWERPC970_HID5_INIT);
+    /* XXX : not implemented */
+    spr_register(env, SPR_L2CR, "L2CR",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_read_generic, NULL,
+                 0x00000000);
+    /* Memory management */
+    /* XXX: not correct */
+    gen_low_BATs(env);
+    /* XXX : not implemented */
+    spr_register(env, SPR_MMUCFG, "MMUCFG",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_read_generic, SPR_NOACCESS,
+                 0x00000000); /* TOFIX */
+    /* XXX : not implemented */
+    spr_register(env, SPR_MMUCSR0, "MMUCSR0",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_read_generic, &spr_write_generic,
+                 0x00000000); /* TOFIX */
+    spr_register(env, SPR_HIOR, "SPR_HIOR",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_read_hior, &spr_write_hior,
+                 0x00000000);
+    spr_register(env, SPR_CTRL, "SPR_CTRL",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_read_generic, &spr_write_generic,
+                 0x00000000);
+    spr_register(env, SPR_UCTRL, "SPR_UCTRL",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_read_generic, &spr_write_generic,
+                 0x00000000);
+    spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
+                 &spr_read_generic, &spr_write_generic,
+                 &spr_read_generic, &spr_write_generic,
+                 0x00000000);
+#if !defined(CONFIG_USER_ONLY)
+    env->slb_nr = 64;
+#endif
+    init_excp_970(env);
+    env->dcache_line_size = 128;
+    env->icache_line_size = 128;
+    /* Allocate hardware IRQ controller */
+    ppc970_irq_init(env);
+    /* Can't find information on what this should be on reset.  This
+     * value is the one used by 74xx processors. */
+    vscr_init(env, 0x00010000);
+}
+
+POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(oc);
+    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+    dc->desc = "POWER5+";
+    pcc->init_proc = init_proc_power5plus;
+    pcc->check_pow = check_pow_970FX;
+    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+                       PPC_FLOAT_STFIWX |
+                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
+                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+                       PPC_64B |
+                       PPC_SEGMENT_64B | PPC_SLBI;
+    pcc->msr_mask = 0x800000000204FF36ULL;
+    pcc->mmu_model = POWERPC_MMU_64B;
+#if defined(CONFIG_SOFTMMU)
+    pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
+#endif
+    pcc->excp_model = POWERPC_EXCP_970;
+    pcc->bus_model = PPC_FLAGS_INPUT_970;
+    pcc->bfd_mach = bfd_mach_ppc64;
+    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
+                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
+                 POWERPC_FLAG_BUS_CLK;
+}
+
 static void init_proc_POWER7 (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
-- 
1.8.1.4

[Qemu-devel] [PATCH for-next 4/4] target-ppc: Add POWER5+ v2.1 CPU model

[Andreas Färber]

Let's avoid -cpu host barfing at this PVR.
Linux recognizes it as "POWER5+ (gs) v2.1".

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 target-ppc/cpu-models.c | 2 ++
 target-ppc/cpu-models.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c
index f2604eb..70157d6 100644
--- a/target-ppc/cpu-models.c
+++ b/target-ppc/cpu-models.c
@@ -1123,6 +1123,8 @@
 #endif
     POWERPC_DEF("POWER5+",       CPU_POWERPC_POWER5P,                POWER5P,
                 "POWER5+")
+    POWERPC_DEF("POWER5+_v2.1",  CPU_POWERPC_POWER5P_v21,            POWER5P,
+                "POWER5+ v2.1")
 #if defined(TODO)
     POWERPC_DEF("POWER6",        CPU_POWERPC_POWER6,                 POWER6,
                 "POWER6")
diff --git a/target-ppc/cpu-models.h b/target-ppc/cpu-models.h
index a844d0d..830ab84 100644
--- a/target-ppc/cpu-models.h
+++ b/target-ppc/cpu-models.h
@@ -548,6 +548,7 @@ enum {
      /* XXX: missing 0x003A0201 */
     CPU_POWERPC_POWER5             = 0x003A0203,
     CPU_POWERPC_POWER5P            = 0x003B0000,
+    CPU_POWERPC_POWER5P_v21        = 0x003B0201,
     CPU_POWERPC_POWER6             = 0x003E0000,
     CPU_POWERPC_POWER6_5           = 0x0F000001, /* POWER6 in POWER5 mode */
     CPU_POWERPC_POWER6A            = 0x0F000002,
-- 
1.8.1.4

[Qemu-devel] Ping for-1.6: [PATCH for-next 0/4] target-ppc: Complete POWER5+ CPU model support

[Andreas Färber]

Am 01.08.2013 03:41, schrieb Andreas Färber:
> Hello,
> 
> This mini-series cleans up, enables and complements POWER5+ support, so that
> KVM with default -cpu host works on POWER5+ (gs) v2.1.

Ping! According to Anthony fixing -cpu host on new models is a bug fix,
so please apply this for POWER5+ v2.1 to work, too.

Thanks,
Andreas

> 
> Thanks to Ben for some valuable hints on how to model POWER5P family!
> 
> Regards,
> Andreas
> 
> Cc: Anthony Liguori <anthony@codemonkey.ws>
> Cc: Alexey Kardashevskiy <aik@ozlabs.ru>
> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Cc: Alexander Graf <agraf@suse.de>
> Cc: qemu-ppc@nongnu.org
> 
> Andreas Färber (4):
>   target-ppc: Turn POWER5gs CPU into alias for POWER5+
>   target-ppc: Turn POWER5gr CPU into alias for POWER5
>   target-ppc: Prepare POWER5P CPU family
>   target-ppc: Add POWER5+ v2.1 CPU model
> 
>  target-ppc/cpu-models.c     |  10 ++---
>  target-ppc/cpu-models.h     |   3 +-
>  target-ppc/translate_init.c | 104 ++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 109 insertions(+), 8 deletions(-)
> 


-- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg

Re: [Qemu-devel] [PATCH for-next 0/4] target-ppc: Complete POWER5+ CPU model support

[Alexander Graf]

On 01.08.2013, at 03:41, Andreas Färber wrote:

> Hello,
> 
> This mini-series cleans up, enables and complements POWER5+ support, so that
> KVM with default -cpu host works on POWER5+ (gs) v2.1.
> 
> Thanks to Ben for some valuable hints on how to model POWER5P family!
> 
> Regards,
> Andreas
> 
> Cc: Anthony Liguori <anthony@codemonkey.ws>
> Cc: Alexey Kardashevskiy <aik@ozlabs.ru>
> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Cc: Alexander Graf <agraf@suse.de>
> Cc: qemu-ppc@nongnu.org

Thanks, applied to ppc-next.


Alex

Re: [Qemu-devel] [PATCH for-next 0/4] target-ppc: Complete POWER5+ CPU model support

[Andreas Färber]

Am 14.08.2013 15:59, schrieb Alexander Graf:
> 
> On 01.08.2013, at 03:41, Andreas Färber wrote:
> 
>> Hello,
>>
>> This mini-series cleans up, enables and complements POWER5+ support, so that
>> KVM with default -cpu host works on POWER5+ (gs) v2.1.
>>
>> Thanks to Ben for some valuable hints on how to model POWER5P family!
>>
>> Regards,
>> Andreas
>>
>> Cc: Anthony Liguori <anthony@codemonkey.ws>
>> Cc: Alexey Kardashevskiy <aik@ozlabs.ru>
>> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>> Cc: Alexander Graf <agraf@suse.de>
>> Cc: qemu-ppc@nongnu.org
> 
> Thanks, applied to ppc-next.

Thanks, but some kind of workflow problem here: Anthony declared adding
CPU models for -cpu host a bugfix and applied both POWER7+ and POWER5+
for 1.6 already.

Cheers,
Andreas

-- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg

Re: [Qemu-devel] [PATCH for-next 0/4] target-ppc: Complete POWER5+ CPU model support

[Anthony Liguori]

Applied.  Thanks.

Regards,

Anthony Liguori