From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34446) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V6Ovj-0007Ve-Er for qemu-devel@nongnu.org; Mon, 05 Aug 2013 13:50:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V6Ovb-0002Df-U2 for qemu-devel@nongnu.org; Mon, 05 Aug 2013 13:50:51 -0400 Received: from mail-qe0-x22a.google.com ([2607:f8b0:400d:c02::22a]:38305) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V6Ovb-0002DQ-Cr for qemu-devel@nongnu.org; Mon, 05 Aug 2013 13:50:43 -0400 Received: by mail-qe0-f42.google.com with SMTP id s14so1918527qeb.15 for ; Mon, 05 Aug 2013 10:50:43 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Mon, 5 Aug 2013 07:49:59 -1000 Message-Id: <1375725002-18526-3-git-send-email-rth@twiddle.net> In-Reply-To: <1375725002-18526-1-git-send-email-rth@twiddle.net> References: <1375725002-18526-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH for-next 2/5] target-alpha: Use goto_tb in call_pal List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Richard Henderson With appropriate flushing when the PALBR changes, the target of a CALL_PAL is so predictable we can chain to it. Signed-off-by: Richard Henderson --- target-alpha/helper.h | 1 + target-alpha/sys_helper.c | 5 +++++ target-alpha/translate.c | 20 ++++++++++++++++++++ 3 files changed, 26 insertions(+) diff --git a/target-alpha/helper.h b/target-alpha/helper.h index 5529c17..732b701 100644 --- a/target-alpha/helper.h +++ b/target-alpha/helper.h @@ -112,6 +112,7 @@ DEF_HELPER_3(stq_c_phys, i64, env, i64, i64) DEF_HELPER_FLAGS_1(tbia, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_2(tbis, TCG_CALL_NO_RWG, void, env, i64) +DEF_HELPER_FLAGS_1(tb_flush, TCG_CALL_NO_RWG, void, env) DEF_HELPER_1(halt, void, i64); diff --git a/target-alpha/sys_helper.c b/target-alpha/sys_helper.c index ce51ed6..97cf9eb 100644 --- a/target-alpha/sys_helper.c +++ b/target-alpha/sys_helper.c @@ -72,6 +72,11 @@ void helper_tbis(CPUAlphaState *env, uint64_t p) tlb_flush_page(env, p); } +void helper_tb_flush(CPUAlphaState *env) +{ + tb_flush(env); +} + void helper_halt(uint64_t restart) { if (restart) { diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 59389a2..f172670 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -1609,6 +1609,17 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int palcode) tcg_temp_free(entry); tcg_temp_free(pc); + + /* Since the destination is running in PALmode, we don't really + need the page permissions check. We'll see the existance of + the page when we create the TB, and we'll flush all TBs if + we change the PAL base register. */ + if (!ctx->singlestep_enabled && !(ctx->tb->cflags & CF_LAST_IO)) { + tcg_gen_goto_tb(0); + tcg_gen_exit_tb((tcg_target_long)ctx->tb); + return EXIT_GOTO_TB; + } + return EXIT_PC_UPDATED; } #endif @@ -1727,6 +1738,15 @@ static ExitStatus gen_mtpr(DisasContext *ctx, int rb, int regno) gen_helper_set_alarm(cpu_env, tmp); break; + case 7: + /* PALBR */ + tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUAlphaState, palbr)); + /* Changing the PAL base register implies un-chaining all of the TBs + that ended with a CALL_PAL. Since the base register usually only + changes during boot, flushing everything works well. */ + gen_helper_tb_flush(cpu_env); + return EXIT_PC_STALE; + default: /* The basic registers are data only, and unknown registers are read-zero, write-ignore. */ -- 1.8.3.1