From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45727) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V6PXD-0003hJ-Rb for qemu-devel@nongnu.org; Mon, 05 Aug 2013 14:29:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V6PX5-00018w-6l for qemu-devel@nongnu.org; Mon, 05 Aug 2013 14:29:35 -0400 Received: from mail-qc0-x234.google.com ([2607:f8b0:400d:c01::234]:50962) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V6PX5-00018r-2w for qemu-devel@nongnu.org; Mon, 05 Aug 2013 14:29:27 -0400 Received: by mail-qc0-f180.google.com with SMTP id j10so1875083qcx.39 for ; Mon, 05 Aug 2013 11:29:26 -0700 (PDT) Received: from pebble.com (cpe-66-91-180-52.hawaii.res.rr.com. [66.91.180.52]) by mx.google.com with ESMTPSA id n8sm574544qez.2.2013.08.05.11.29.25 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 05 Aug 2013 11:29:26 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Mon, 5 Aug 2013 08:28:35 -1000 Message-Id: <1375727330-30515-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH for-next 00/15] Collection of improvements for tcg/ppc64 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org About half of these patches are focused on reducing the number of full 64-bit constants that need to be generated for addresses: E.g. patch 5, looking through the function descriptor. If the program is built --disable-pie, the elements of the function descriptors are all 32-bit constants. E.g. the end result of indirect jump threading + TCG_REG_TB. Before, we reserve 6 insn slots to generate the full 64-bit address. After, we use 2 insns -- addis + ld -- to load the full 64-bit address from the indirection slot. The second patch could probably be reverted. I'd planned to be able to use the same conditional call + tail call scheme as ARM, but I'd forgotten the need for a conditional store to go along with that. OTOH, it might still turn out to be useful somewhere. r~ Richard Henderson (15): tcg-ppc64: Avoid code for nop move tcg-ppc64: Add an LK argument to tcg_out_call tcg-ppc64: Use the branch absolute instruction when possible tcg-ppc64: Don't load the static chain from TCG tcg-ppc64: Look through the function descriptor when profitable tcg-ppc64: Move AREG0 to r31 tcg-ppc64: Tidy register allocation order tcg-ppc64: Create PowerOpcode tcg-ppc64: Handle long offsets better tcg-ppc64: Use indirect jump threading tcg-ppc64: Setup TCG_REG_TB tcg-ppc64: Use TCG_REG_TB in tcg_out_movi and tcg_out_mem_long tcg-ppc64: Tidy tcg_target_qemu_prologue tcg-ppc64: Streamline tcg_out_tlb_read tcg-ppc64: Implement CONFIG_QEMU_LDST_OPTIMIZATION configure | 2 +- include/exec/exec-all.h | 7 +- tcg/ppc64/tcg-target.c | 1079 ++++++++++++++++++++++++++--------------------- tcg/ppc64/tcg-target.h | 2 +- 4 files changed, 598 insertions(+), 492 deletions(-) -- 1.8.3.1