From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45955) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V6PXZ-00048N-Pc for qemu-devel@nongnu.org; Mon, 05 Aug 2013 14:30:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V6PXT-0001Ge-Aw for qemu-devel@nongnu.org; Mon, 05 Aug 2013 14:29:57 -0400 Received: from mail-qe0-x235.google.com ([2607:f8b0:400d:c02::235]:50979) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V6PXT-0001GT-6X for qemu-devel@nongnu.org; Mon, 05 Aug 2013 14:29:51 -0400 Received: by mail-qe0-f53.google.com with SMTP id f6so1925653qej.12 for ; Mon, 05 Aug 2013 11:29:50 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Mon, 5 Aug 2013 08:28:45 -1000 Message-Id: <1375727330-30515-11-git-send-email-rth@twiddle.net> In-Reply-To: <1375727330-30515-1-git-send-email-rth@twiddle.net> References: <1375727330-30515-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH for-next 10/15] tcg-ppc64: Use indirect jump threading List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: "Vassili Karpov (malc)" , Richard Henderson We were always doing an indirect jump anyway, and the sequence is never longer than the 6 insns we were reserving for the direct jump. Futher cleanups will reduce the length of the constant address load. Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 3 ++- tcg/ppc64/tcg-target.c | 26 ++++++++------------------ 2 files changed, 10 insertions(+), 19 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index b3402a1..26c3553 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -126,7 +126,8 @@ static inline void tlb_flush(CPUArchState *env, int flush_global) #define CODE_GEN_AVG_BLOCK_SIZE 64 #endif -#if defined(__arm__) || defined(_ARCH_PPC) \ +#if defined(__arm__) \ + || (defined(__powerpc__) && !defined(__powerpc64__)) \ || defined(__x86_64__) || defined(__i386__) \ || defined(__sparc__) || defined(__aarch64__) \ || defined(CONFIG_TCG_INTERPRETER) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index e9c41fb..f69bc8f 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -1440,17 +1440,6 @@ static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond, } } -void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr) -{ - TCGContext s; - unsigned long patch_size; - - s.code_ptr = (uint8_t *) jmp_addr; - tcg_out_b (&s, 0, addr); - patch_size = s.code_ptr - (uint8_t *) jmp_addr; - flush_icache_range (jmp_addr, jmp_addr + patch_size); -} - static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args) { @@ -1464,13 +1453,14 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_goto_tb: if (s->tb_jmp_offset) { - /* direct jump method */ - - s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf; - s->code_ptr += 28; - } - else { - tcg_abort (); + /* Direct jump method. */ + tcg_abort(); + } else { + /* Indirect jump method. */ + tcg_out_mem_long(s, LD, LDX, TCG_REG_R0, TCG_REG_R0, + (tcg_target_long)(s->tb_next + args[0])); + tcg_out32(s, MTSPR | RS(TCG_REG_R0) | CTR); + tcg_out32(s, BCCTR | BO_ALWAYS); } s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf; break; -- 1.8.3.1