From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43644) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V7TMV-0005Wb-03 for qemu-devel@nongnu.org; Thu, 08 Aug 2013 12:47:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V7TMP-0000Ro-Pq for qemu-devel@nongnu.org; Thu, 08 Aug 2013 12:46:54 -0400 Received: from mail-qa0-x22b.google.com ([2607:f8b0:400d:c00::22b]:38273) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V7TMP-0000RZ-GR for qemu-devel@nongnu.org; Thu, 08 Aug 2013 12:46:49 -0400 Received: by mail-qa0-f43.google.com with SMTP id cl20so410277qab.9 for ; Thu, 08 Aug 2013 09:46:49 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Thu, 8 Aug 2013 06:46:10 -1000 Message-Id: <1375980370-27822-2-git-send-email-rth@twiddle.net> In-Reply-To: <1375980370-27822-1-git-send-email-rth@twiddle.net> References: <1375980370-27822-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PULL for-1.6] tcg/mips: fix invalid op definition errors List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aliguori@us.ibm.com, James Hogan , Aurelien Jarno , Richard Henderson From: James Hogan tcg/mips/tcg-target.h defines various operations conditionally depending upon the isa revision, however these operations are included in mips_op_defs[] unconditionally resulting in the following runtime errors if CONFIG_DEBUG_TCG is defined: Invalid op definition for movcond_i32 Invalid op definition for rotl_i32 Invalid op definition for rotr_i32 Invalid op definition for deposit_i32 Invalid op definition for bswap16_i32 Invalid op definition for bswap32_i32 tcg/tcg.c:1196: tcg fatal error Fix with ifdefs like the i386 backend does for movcond_i32. Signed-off-by: James Hogan Cc: Aurelien Jarno Cc: Richard Henderson Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c index 373c364..793532e 100644 --- a/tcg/mips/tcg-target.c +++ b/tcg/mips/tcg-target.c @@ -1617,19 +1617,29 @@ static const TCGTargetOpDef mips_op_defs[] = { { INDEX_op_shl_i32, { "r", "rZ", "ri" } }, { INDEX_op_shr_i32, { "r", "rZ", "ri" } }, { INDEX_op_sar_i32, { "r", "rZ", "ri" } }, +#if TCG_TARGET_HAS_rot_i32 { INDEX_op_rotr_i32, { "r", "rZ", "ri" } }, { INDEX_op_rotl_i32, { "r", "rZ", "ri" } }, +#endif +#if TCG_TARGET_HAS_bswap16_i32 { INDEX_op_bswap16_i32, { "r", "r" } }, +#endif +#if TCG_TARGET_HAS_bswap32_i32 { INDEX_op_bswap32_i32, { "r", "r" } }, +#endif { INDEX_op_ext8s_i32, { "r", "rZ" } }, { INDEX_op_ext16s_i32, { "r", "rZ" } }, +#if TCG_TARGET_HAS_deposit_i32 { INDEX_op_deposit_i32, { "r", "0", "rZ" } }, +#endif { INDEX_op_brcond_i32, { "rZ", "rZ" } }, +#if TCG_TARGET_HAS_movcond_i32 { INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rZ", "0" } }, +#endif { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } }, { INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rZ", "rZ" } }, -- 1.8.3.1