From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47388) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V8n3j-0007Bp-Gf for qemu-devel@nongnu.org; Mon, 12 Aug 2013 04:01:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V8n3d-0006TG-7J for qemu-devel@nongnu.org; Mon, 12 Aug 2013 04:00:59 -0400 Received: from ozlabs.org ([203.10.76.45]:50064) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V8n3c-0006Su-S1 for qemu-devel@nongnu.org; Mon, 12 Aug 2013 04:00:53 -0400 From: Rusty Russell Date: Mon, 12 Aug 2013 17:29:22 +0930 Message-Id: <1376294363-4650-3-git-send-email-rusty@rustcorp.com.au> In-Reply-To: <1376294363-4650-1-git-send-email-rusty@rustcorp.com.au> References: <1376294363-4650-1-git-send-email-rusty@rustcorp.com.au> Subject: [Qemu-devel] [PATCH 2/8] target-ppc: ppc64 target's virtio can be either endian. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Rusty Russell We base it on the OS endian, as reflected by the endianness of the interrupt vectors. Suggested-by: Benjamin Herrenschmidt Signed-off-by: Rusty Russell --- target-ppc/misc_helper.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target-ppc/misc_helper.c b/target-ppc/misc_helper.c index 616aab6..6c97c81 100644 --- a/target-ppc/misc_helper.c +++ b/target-ppc/misc_helper.c @@ -20,6 +20,7 @@ #include "helper.h" #include "helper_regs.h" +#include "hw/virtio/virtio.h" /*****************************************************************************/ /* SPR accesses */ @@ -116,3 +117,11 @@ void ppc_store_msr(CPUPPCState *env, target_ulong value) { hreg_store_msr(env, value, 0); } + +bool virtio_get_byteswap(void) +{ + PowerPCCPU *cp = POWERPC_CPU(first_cpu); + CPUPPCState *env = &cp->env; + + return env->spr[SPR_LPCR] & LPCR_ILE; +} -- 1.8.1.2