[Qemu-devel] [RFC 07/14] tcg-aarch64: Support movcond

[Richard Henderson <rth@twiddle.net>]

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/aarch64/tcg-target.c | 19 ++++++++++++++++++-
 tcg/aarch64/tcg-target.h |  4 ++--
 2 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 88bbfd2..f0febc9 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -267,6 +267,7 @@ typedef enum {
     INSN_EXTR  = 0x13800000,
 
     /* Conditional select instructions */
+    INSN_CSEL  = 0x1a800000,
     INSN_CSINC = 0x1a800400,
 
     /* Branch instructions */
@@ -673,6 +674,13 @@ static inline void tcg_out_cset(TCGContext *s, AArch64Ext ext,
     tcg_out32(s, base | ext | cond << 12 | rd);
 }
 
+static inline void tcg_out_csel(TCGContext *s, AArch64Ext ext, TCGReg rd,
+                                TCGReg rn, TCGReg rm, TCGCond c)
+{
+    unsigned int cond = tcg_cond_to_aarch64[c];
+    tcg_out32(s, INSN_CSEL | ext | rm << 16 | cond << 12 | rn << 5 | rd);
+}
+
 static inline void tcg_out_goto(TCGContext *s, tcg_target_long target)
 {
     tcg_target_long offset;
@@ -1453,6 +1461,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
         tcg_out_cset(s, 0, args[0], args[3]);
         break;
 
+    case INDEX_op_movcond_i64:
+        ext = E64; /* fall through */
+    case INDEX_op_movcond_i32:
+        tcg_out_cmp(s, ext, args[1], args[2], const_args[2]);
+        tcg_out_csel(s, ext, args[0], REG0(3), REG0(4), args[5]);
+        break;
+
     case INDEX_op_qemu_ld8u:
         tcg_out_qemu_ld(s, args, 0 | 0);
         break;
@@ -1600,9 +1615,11 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
     { INDEX_op_rotr_i64, { "r", "r", "ri" } },
 
     { INDEX_op_brcond_i32, { "r", "rC" } },
-    { INDEX_op_setcond_i32, { "r", "r", "rC" } },
     { INDEX_op_brcond_i64, { "r", "rC" } },
+    { INDEX_op_setcond_i32, { "r", "r", "rC" } },
     { INDEX_op_setcond_i64, { "r", "r", "rC" } },
+    { INDEX_op_movcond_i32, { "r", "r", "rC", "rZ", "rZ" } },
+    { INDEX_op_movcond_i64, { "r", "r", "rC", "rZ", "rZ" } },
 
     { INDEX_op_qemu_ld8u, { "r", "l" } },
     { INDEX_op_qemu_ld8s, { "r", "l" } },
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index ffe9429..7d87870 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -56,7 +56,7 @@ typedef enum {
 #define TCG_TARGET_HAS_nand_i32         0
 #define TCG_TARGET_HAS_nor_i32          0
 #define TCG_TARGET_HAS_deposit_i32      0
-#define TCG_TARGET_HAS_movcond_i32      0
+#define TCG_TARGET_HAS_movcond_i32      1
 #define TCG_TARGET_HAS_add2_i32         0
 #define TCG_TARGET_HAS_sub2_i32         0
 #define TCG_TARGET_HAS_mulu2_i32        0
@@ -82,7 +82,7 @@ typedef enum {
 #define TCG_TARGET_HAS_nand_i64         0
 #define TCG_TARGET_HAS_nor_i64          0
 #define TCG_TARGET_HAS_deposit_i64      0
-#define TCG_TARGET_HAS_movcond_i64      0
+#define TCG_TARGET_HAS_movcond_i64      1
 #define TCG_TARGET_HAS_add2_i64         0
 #define TCG_TARGET_HAS_sub2_i64         0
 #define TCG_TARGET_HAS_mulu2_i64        0
-- 
1.8.3.1