From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57905) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VBnkc-0003CQ-9G for qemu-devel@nongnu.org; Tue, 20 Aug 2013 11:21:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VBnkM-0000Ym-GP for qemu-devel@nongnu.org; Tue, 20 Aug 2013 11:21:42 -0400 Received: from cantor2.suse.de ([195.135.220.15]:59742 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VBnkM-0000Xa-1r for qemu-devel@nongnu.org; Tue, 20 Aug 2013 11:21:26 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Tue, 20 Aug 2013 17:21:11 +0200 Message-Id: <1377012076-7035-20-git-send-email-afaerber@suse.de> In-Reply-To: <1377012076-7035-1-git-send-email-afaerber@suse.de> References: <1377012076-7035-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH v3 19/24] arm11mpcore: Convert ARM11MPCorePriveState to QOM realize List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook Embed child devices and replace SysBus initfn with realizefn. Signed-off-by: Andreas F=C3=A4rber --- hw/cpu/arm11mpcore.c | 84 ++++++++++++++++++++++++++++++++++------------= ------ 1 file changed, 56 insertions(+), 28 deletions(-) diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu/arm11mpcore.c index 9ab2bf5..0fb14e1 100644 --- a/hw/cpu/arm11mpcore.c +++ b/hw/cpu/arm11mpcore.c @@ -9,6 +9,8 @@ =20 #include "hw/sysbus.h" #include "hw/misc/arm11scu.h" +#include "hw/intc/arm_gic.h" +#include "hw/timer/arm_mptimer.h" #include "qemu/timer.h" =20 /* MPCore private memory region. */ @@ -22,12 +24,12 @@ typedef struct ARM11MPCorePriveState { =20 uint32_t num_cpu; MemoryRegion container; - DeviceState *mptimer; - DeviceState *wdtimer; - DeviceState *gic; uint32_t num_irq; =20 ARM11SCUState scu; + GICState gic; + ARMMPTimerState mptimer; + ARMMPTimerState wdtimer; } ARM11MPCorePriveState; =20 /* Per-CPU private memory mapped IO. */ @@ -36,16 +38,18 @@ typedef struct ARM11MPCorePriveState { static void mpcore_priv_set_irq(void *opaque, int irq, int level) { ARM11MPCorePriveState *s =3D (ARM11MPCorePriveState *)opaque; - qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); + + qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); } =20 static void mpcore_priv_map_setup(ARM11MPCorePriveState *s) { int i; SysBusDevice *scubusdev =3D SYS_BUS_DEVICE(&s->scu); - SysBusDevice *gicbusdev =3D SYS_BUS_DEVICE(s->gic); - SysBusDevice *timerbusdev =3D SYS_BUS_DEVICE(s->mptimer); - SysBusDevice *wdtbusdev =3D SYS_BUS_DEVICE(s->wdtimer); + DeviceState *gicdev =3D DEVICE(&s->gic); + SysBusDevice *gicbusdev =3D SYS_BUS_DEVICE(&s->gic); + SysBusDevice *timerbusdev =3D SYS_BUS_DEVICE(&s->mptimer); + SysBusDevice *wdtbusdev =3D SYS_BUS_DEVICE(&s->wdtimer); =20 memory_region_add_subregion(&s->container, 0, sysbus_mmio_get_region(scubusdev, 0)); @@ -76,44 +80,58 @@ static void mpcore_priv_map_setup(ARM11MPCorePriveSta= te *s) for (i =3D 0; i < s->num_cpu; i++) { int ppibase =3D (s->num_irq - 32) + i * 32; sysbus_connect_irq(timerbusdev, i, - qdev_get_gpio_in(s->gic, ppibase + 29)); + qdev_get_gpio_in(gicdev, ppibase + 29)); sysbus_connect_irq(wdtbusdev, i, - qdev_get_gpio_in(s->gic, ppibase + 30)); + qdev_get_gpio_in(gicdev, ppibase + 30)); } } =20 -static int mpcore_priv_init(SysBusDevice *sbd) +static void mpcore_priv_realize(DeviceState *dev, Error **errp) { - DeviceState *dev =3D DEVICE(sbd); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); ARM11MPCorePriveState *s =3D ARM11MPCORE_PRIV(dev); DeviceState *scudev =3D DEVICE(&s->scu); + DeviceState *gicdev =3D DEVICE(&s->gic); + DeviceState *mptimerdev =3D DEVICE(&s->mptimer); + DeviceState *wdtimerdev =3D DEVICE(&s->wdtimer); + Error *err =3D NULL; =20 qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); - qdev_init_nofail(scudev); + object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } =20 - s->gic =3D qdev_create(NULL, "arm_gic"); - qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); - qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); - /* Request the legacy 11MPCore GIC behaviour: */ - qdev_prop_set_uint32(s->gic, "revision", 0); - qdev_init_nofail(s->gic); + qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); + qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); + object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } =20 /* Pass through outbound IRQ lines from the GIC */ - sysbus_pass_irq(sbd, SYS_BUS_DEVICE(s->gic)); + sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->gic)); =20 /* Pass through inbound GPIO lines to the GIC */ qdev_init_gpio_in(dev, mpcore_priv_set_irq, s->num_irq - 32); =20 - s->mptimer =3D qdev_create(NULL, "arm_mptimer"); - qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu); - qdev_init_nofail(s->mptimer); + qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu); + object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err= ); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } =20 - s->wdtimer =3D qdev_create(NULL, "arm_mptimer"); - qdev_prop_set_uint32(s->wdtimer, "num-cpu", s->num_cpu); - qdev_init_nofail(s->wdtimer); + qdev_prop_set_uint32(wdtimerdev, "num-cpu", s->num_cpu); + object_property_set_bool(OBJECT(&s->wdtimer), true, "realized", &err= ); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } =20 mpcore_priv_map_setup(s); - return 0; } =20 static void mpcore_priv_initfn(Object *obj) @@ -127,6 +145,17 @@ static void mpcore_priv_initfn(Object *obj) =20 object_initialize(&s->scu, TYPE_ARM11_SCU); qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default()); + + object_initialize(&s->gic, TYPE_ARM_GIC); + qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); + /* Request the legacy 11MPCore GIC behaviour: */ + qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 0); + + object_initialize(&s->mptimer, TYPE_ARM_MPTIMER); + qdev_set_parent_bus(DEVICE(&s->mptimer), sysbus_get_default()); + + object_initialize(&s->wdtimer, TYPE_ARM_MPTIMER); + qdev_set_parent_bus(DEVICE(&s->wdtimer), sysbus_get_default()); } =20 #define TYPE_REALVIEW_MPCORE_RIRQ "realview_mpcore" @@ -237,9 +266,8 @@ static Property mpcore_priv_properties[] =3D { static void mpcore_priv_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); - SysBusDeviceClass *k =3D SYS_BUS_DEVICE_CLASS(klass); =20 - k->init =3D mpcore_priv_init; + dc->realize =3D mpcore_priv_realize; dc->props =3D mpcore_priv_properties; } =20 --=20 1.8.1.4