From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57886) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VBnka-0003CJ-P1 for qemu-devel@nongnu.org; Tue, 20 Aug 2013 11:21:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VBnkM-0000YR-Bu for qemu-devel@nongnu.org; Tue, 20 Aug 2013 11:21:40 -0400 Received: from cantor2.suse.de ([195.135.220.15]:59744 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VBnkM-0000Xf-2d for qemu-devel@nongnu.org; Tue, 20 Aug 2013 11:21:26 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Tue, 20 Aug 2013 17:21:14 +0200 Message-Id: <1377012076-7035-23-git-send-email-afaerber@suse.de> In-Reply-To: <1377012076-7035-1-git-send-email-afaerber@suse.de> References: <1377012076-7035-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH v3 22/24] arm11mpcore: Convert mpcore_rirq_state to QOM realize List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook Embed ARM11MPCorePriveState and RealViewGICState and replace SysBus initfn with realizefn. Signed-off-by: Andreas F=C3=A4rber --- hw/cpu/arm11mpcore.c | 58 +++++++++++++++++++++++++++++++++++++++-------= ------ 1 file changed, 44 insertions(+), 14 deletions(-) diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu/arm11mpcore.c index 0fb14e1..4872205 100644 --- a/hw/cpu/arm11mpcore.c +++ b/hw/cpu/arm11mpcore.c @@ -10,6 +10,7 @@ #include "hw/sysbus.h" #include "hw/misc/arm11scu.h" #include "hw/intc/arm_gic.h" +#include "hw/intc/realview_gic.h" #include "hw/timer/arm_mptimer.h" #include "qemu/timer.h" =20 @@ -168,10 +169,12 @@ static void mpcore_priv_initfn(Object *obj) typedef struct { SysBusDevice parent_obj; =20 - SysBusDevice *priv; qemu_irq cpuic[32]; qemu_irq rvic[4][64]; uint32_t num_cpu; + + ARM11MPCorePriveState priv; + RealViewGICState gic[4]; } mpcore_rirq_state; =20 /* Map baseboard IRQs onto CPU IRQ lines. */ @@ -198,34 +201,61 @@ static void mpcore_rirq_set_irq(void *opaque, int i= rq, int level) } } =20 -static int realview_mpcore_init(SysBusDevice *sbd) +static void realview_mpcore_realize(DeviceState *dev, Error **errp) { - DeviceState *dev =3D DEVICE(sbd); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); mpcore_rirq_state *s =3D REALVIEW_MPCORE_RIRQ(dev); + DeviceState *priv =3D DEVICE(&s->priv); DeviceState *gic; - DeviceState *priv; + SysBusDevice *gicbusdev; + Error *err =3D NULL; int n; int i; =20 - priv =3D qdev_create(NULL, TYPE_ARM11MPCORE_PRIV); qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu); - qdev_init_nofail(priv); - s->priv =3D SYS_BUS_DEVICE(priv); - sysbus_pass_irq(sbd, s->priv); + object_property_set_bool(OBJECT(&s->priv), true, "realized", &err); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } + sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->priv)); for (i =3D 0; i < 32; i++) { s->cpuic[i] =3D qdev_get_gpio_in(priv, i); } /* ??? IRQ routing is hardcoded to "normal" mode. */ for (n =3D 0; n < 4; n++) { - gic =3D sysbus_create_simple("realview_gic", 0x10040000 + n * 0x= 10000, - s->cpuic[10 + n]); + object_property_set_bool(OBJECT(&s->gic[n]), true, "realized", &= err); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } + gic =3D DEVICE(&s->gic[n]); + gicbusdev =3D SYS_BUS_DEVICE(&s->gic[n]); + sysbus_mmio_map(gicbusdev, 0, 0x10040000 + n * 0x10000); + sysbus_connect_irq(gicbusdev, 0, s->cpuic[10 + n]); for (i =3D 0; i < 64; i++) { s->rvic[n][i] =3D qdev_get_gpio_in(gic, i); } } qdev_init_gpio_in(dev, mpcore_rirq_set_irq, 64); - sysbus_init_mmio(sbd, sysbus_mmio_get_region(s->priv, 0)); - return 0; +} + +static void mpcore_rirq_init(Object *obj) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + mpcore_rirq_state *s =3D REALVIEW_MPCORE_RIRQ(obj); + SysBusDevice *privbusdev; + int i; + + object_initialize(&s->priv, TYPE_ARM11MPCORE_PRIV); + qdev_set_parent_bus(DEVICE(&s->priv), sysbus_get_default()); + privbusdev =3D SYS_BUS_DEVICE(&s->priv); + sysbus_init_mmio(sbd, sysbus_mmio_get_region(privbusdev, 0)); + + for (i =3D 0; i < 4; i++) { + object_initialize(&s->gic[i], TYPE_REALVIEW_GIC); + qdev_set_parent_bus(DEVICE(&s->gic[i]), sysbus_get_default()); + } } =20 static Property mpcore_rirq_properties[] =3D { @@ -236,9 +266,8 @@ static Property mpcore_rirq_properties[] =3D { static void mpcore_rirq_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); - SysBusDeviceClass *k =3D SYS_BUS_DEVICE_CLASS(klass); =20 - k->init =3D realview_mpcore_init; + dc->realize =3D realview_mpcore_realize; dc->props =3D mpcore_rirq_properties; } =20 @@ -246,6 +275,7 @@ static const TypeInfo mpcore_rirq_info =3D { .name =3D TYPE_REALVIEW_MPCORE_RIRQ, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(mpcore_rirq_state), + .instance_init =3D mpcore_rirq_init, .class_init =3D mpcore_rirq_class_init, }; =20 --=20 1.8.1.4