From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60231) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VBxpe-0003Vb-S8 for qemu-devel@nongnu.org; Tue, 20 Aug 2013 22:07:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VBxpW-0007vu-6A for qemu-devel@nongnu.org; Tue, 20 Aug 2013 22:07:34 -0400 Received: from mail-pd0-x231.google.com ([2607:f8b0:400e:c02::231]:35716) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VBxpV-0007vn-Vb for qemu-devel@nongnu.org; Tue, 20 Aug 2013 22:07:26 -0400 Received: by mail-pd0-f177.google.com with SMTP id y10so1180235pdj.8 for ; Tue, 20 Aug 2013 19:07:25 -0700 (PDT) From: Jia Liu Date: Wed, 21 Aug 2013 10:06:50 +0800 Message-Id: <1377050811-11116-3-git-send-email-proljc@gmail.com> In-Reply-To: <1377050811-11116-1-git-send-email-proljc@gmail.com> References: <1377050811-11116-1-git-send-email-proljc@gmail.com> Content-Type: text/plain; charset="utf-8" Subject: [Qemu-devel] [PULL 2/3] hw/openrisc: Fix masking in openrisc_pic_cpu_handler() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, aliguori@us.ibm.com, xi.wang@gmail.com Consider the masking of PICSR and PICMR: ((cpu->env.picsr && (1 << i)) && (cpu->env.picmr && (1 << i))) To correctly mask bits, we should use the bitwise AND "&" rather than the logical AND "&&". Also, the loop is not necessary for masking. Simply use (cpu->env.picsr & cpu->env.picmr). Signed-off-by: Xi Wang Acked-by: Jia Liu --- hw/openrisc/pic_cpu.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/hw/openrisc/pic_cpu.c b/hw/openrisc/pic_cpu.c index ca0b7c1..3fcee02 100644 --- a/hw/openrisc/pic_cpu.c +++ b/hw/openrisc/pic_cpu.c @@ -26,7 +26,6 @@ static void openrisc_pic_cpu_handler(void *opaque, int irq, int level) { OpenRISCCPU *cpu = (OpenRISCCPU *)opaque; CPUState *cs = CPU(cpu); - int i; uint32_t irq_bit = 1 << irq; if (irq > 31 || irq < 0) { @@ -39,13 +38,11 @@ static void openrisc_pic_cpu_handler(void *opaque, int irq, int level) cpu->env.picsr &= ~irq_bit; } - for (i = 0; i < 32; i++) { - if ((cpu->env.picsr && (1 << i)) && (cpu->env.picmr && (1 << i))) { - cpu_interrupt(cs, CPU_INTERRUPT_HARD); - } else { - cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); - cpu->env.picsr &= ~(1 << i); - } + if (cpu->env.picsr & cpu->env.picmr) { + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + cpu->env.picsr = 0; } } -- 1.7.12.4 (Apple Git-37)