From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60461) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VCZcN-0004lC-RH for qemu-devel@nongnu.org; Thu, 22 Aug 2013 14:28:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VCZcK-0006y3-Ur for qemu-devel@nongnu.org; Thu, 22 Aug 2013 14:28:23 -0400 Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa ([2001:8b0:1d0::1]:59406 helo=mnementh.archaic.org.uk) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VCZcK-0006vb-O0 for qemu-devel@nongnu.org; Thu, 22 Aug 2013 14:28:20 -0400 From: Peter Maydell Date: Thu, 22 Aug 2013 19:28:10 +0100 Message-Id: <1377196092-7482-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [RFC 0/2] Implement versatile PCI IMAP registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: "Michael S. Tsirkin" , patches@linaro.org This RFC patchset implements the versatile PCI controller's IMAP registers correctly. These registers deal with the mapping of the system address space into PCI space, ie they control what bits of RAM are written to by bus-mastering PCI devices. (At the moment we just use the system memory space as the PCI DMA address space, which means that there is always a flat 1:1 mapping, which is what Linux happens to expect.) This is an RFC for two reasons: (1) I needed to add support to the PCI core code for "allow this device to respond if its MMIO BARs are programmed for address zero", and I'm not sure I did this the right way. (2) since the core code doesn't forbid a PCI device from doing a bus-master access back into its own MMIO bars, it's possible for a guest to configure the controller into a hall-of-mirrors mapping of the PCI and system memory spaces into each other such that an access would loop infinitely. This will probably result in infinite recursion in QEMU in render_memory_region(). Suggestions for how to avoid this welcome... thanks -- PMM Peter Maydell (2): hw/pci: Add PCI capability to allow BARs at 0 hw/pci-host/versatile: Implement IMAP registers hw/pci-host/versatile.c | 72 +++++++++++++++++++++++++++++++++++++++++++++++ hw/pci/pci.c | 3 +- include/hw/pci/pci.h | 3 ++ 3 files changed, 77 insertions(+), 1 deletion(-) -- 1.7.9.5