From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35335) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VCu9r-0005uq-CT for qemu-devel@nongnu.org; Fri, 23 Aug 2013 12:24:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VCu9n-0001OQ-S1 for qemu-devel@nongnu.org; Fri, 23 Aug 2013 12:24:19 -0400 Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa ([2001:8b0:1d0::1]:59451 helo=mnementh.archaic.org.uk) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VCu9n-0001O7-Ka for qemu-devel@nongnu.org; Fri, 23 Aug 2013 12:24:15 -0400 From: Peter Maydell Date: Fri, 23 Aug 2013 17:12:39 +0100 Message-Id: <1377274359-8707-3-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1377274359-8707-1-git-send-email-peter.maydell@linaro.org> References: <1377274359-8707-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 2/2] target-arm: Avoid "1 << 31" undefined behaviour List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: patches@linaro.org Avoid the undefined behaviour of "1 << 31" by using 1U to make the shift be of an unsigned value rather than shifting into the sign bit of a signed integer. Signed-off-by: Peter Maydell --- target-arm/cpu.h | 2 +- target-arm/helper.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index f2abdf3..f3bd501 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -285,7 +285,7 @@ int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw, #define CPSR_V (1 << 28) #define CPSR_C (1 << 29) #define CPSR_Z (1 << 30) -#define CPSR_N (1 << 31) +#define CPSR_N (1U << 31) #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) diff --git a/target-arm/helper.c b/target-arm/helper.c index f4e1b06..b13edf1 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -972,7 +972,7 @@ static int par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) static inline bool extended_addresses_enabled(CPUARMState *env) { return arm_feature(env, ARM_FEATURE_LPAE) - && (env->cp15.c2_control & (1 << 31)); + && (env->cp15.c2_control & (1U << 31)); } static int ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) @@ -1385,7 +1385,7 @@ static int mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri, * so these bits always RAZ. */ if (arm_feature(env, ARM_FEATURE_V7MP)) { - mpidr |= (1 << 31); + mpidr |= (1U << 31); /* Cores which are uniprocessor (non-coherent) * but still implement the MP extensions set * bit 30. (For instance, A9UP.) However we do -- 1.7.9.5