From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58520) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VCxgu-0002oN-SB for qemu-devel@nongnu.org; Fri, 23 Aug 2013 16:10:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VCxgn-0005tG-Ia for qemu-devel@nongnu.org; Fri, 23 Aug 2013 16:10:40 -0400 Received: from mail-pd0-f178.google.com ([209.85.192.178]:48198) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VCxgn-0005sh-CG for qemu-devel@nongnu.org; Fri, 23 Aug 2013 16:10:33 -0400 Received: by mail-pd0-f178.google.com with SMTP id w10so1073575pde.23 for ; Fri, 23 Aug 2013 13:10:32 -0700 (PDT) From: Christoffer Dall Date: Fri, 23 Aug 2013 13:10:20 -0700 Message-Id: <1377288624-7418-2-git-send-email-christoffer.dall@linaro.org> In-Reply-To: <1377288624-7418-1-git-send-email-christoffer.dall@linaro.org> References: <1377288624-7418-1-git-send-email-christoffer.dall@linaro.org> Subject: [Qemu-devel] [PATCH 1/5] hw: arm_gic: Fix gic_set_irq handling List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: linaro-kernel@lists.linaro.org, kvmarm@lists.cs.columbia.edu, Christoffer Dall , patches@linaro.org For some reason only edge-triggered or enabled level-triggered interrupts would set the pending state of a raised IRQ. This is not in compliance with the specs, which indicate that the pending state is separate from the enabled state, which only controls if a pending interrupt is actually forwarded to the CPU interface. Therefore, simply always set the pending state on a rising edge, but only clear the pending state of falling edge if the interrupt is level triggered. Signed-off-by: Christoffer Dall --- hw/intc/arm_gic.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index d431b7a..bff3f9e 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -128,11 +128,12 @@ static void gic_set_irq(void *opaque, int irq, int level) if (level) { GIC_SET_LEVEL(irq, cm); - if (GIC_TEST_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) { - DPRINTF("Set %d pending mask %x\n", irq, target); - GIC_SET_PENDING(irq, target); - } + DPRINTF("Set %d pending mask %x\n", irq, target); + GIC_SET_PENDING(irq, target); } else { + if (!GIC_TEST_TRIGGER(irq)) { + gic_clear_pending(s, irq, target, 0); + } GIC_CLEAR_LEVEL(irq, cm); } gic_update(s); -- 1.7.10.4